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EP-4739024-A1 - TRANSISTOR STRUCTURE, VERTICAL NAND FLASH MEMORY, AND METHOD

EP4739024A1EP 4739024 A1EP4739024 A1EP 4739024A1EP-4739024-A1

Abstract

A transistor structure for a vertical NAND flash memory device is provided. The transistor structure comprises a semiconductor channel layer, a first auxiliary layer and a second auxiliary layer arranged at two opposite sides of the semiconductor channel layer along a first axis, and each of the first auxiliary layer and the second auxiliary layer comprises a first material having a first relative permittivity, the first relative permittivity being larger than 1 and lower than 3.9. The transistor structure further comprises: a first dielectric layer arranged above the semiconductor channel layer, the first auxiliary layer and the first auxiliary layer along a second axis that is perpendicular to the first axis; a charge storage layer arranged on the first dielectric layer; a second dielectric layer arranged on the charge storage layer; and a gate layer arranged on the second dielectric layer.

Inventors

  • Verreck, Devin
  • RACHIDI, Sana
  • ROSMEULEN, MAARTEN

Assignees

  • Imec VZW

Dates

Publication Date
20260506
Application Date
20241105

Claims (10)

  1. A transistor structure (10) for a vertical NAND flash memory device, wherein the transistor structure (10) comprises: a semiconductor channel layer (12); a first auxiliary layer (13-1) and a second auxiliary layer (13-2) arranged on two opposite sides of the semiconductor channel layer (12) along a first axis, wherein each of the first auxiliary layer (13-1) and the second auxiliary layer (13-2) comprises a first material having a first relative permittivity, the first relative permittivity being larger than 1 and lower than 3.9; a first dielectric layer (14) arranged above the semiconductor channel layer (12), the first auxiliary layer (13-1) and the second auxiliary layer (13-2), along a second axis perpendicular to the first axis; a charge storage layer (15) arranged on the first dielectric layer (14); a second dielectric layer (16) arranged on the charge storage layer (15); and a gate layer (17) arranged on the second dielectric layer (16).
  2. The transistor structure (10) according to claim 1, wherein: the first auxiliary layer (13-1) partially extends into the first dielectric layer (14) along the second axis; and/or the second auxiliary layer (13-2) partially extends into the first dielectric layer (14) along the second axis.
  3. The transistor structure (10) according to claim 1 or 2, wherein: the first material is or comprises air; or the first material comprises a porous material.
  4. The transistor structure (10) according to any one of the preceding claims, wherein: the first dielectric layer (14) comprises a second material having a second relative permittivity, the second relative permittivity being larger than the first relative permittivity.
  5. The transistor structure (10) according to any one of the preceding claims, wherein: a cross section of the semiconductor channel layer (12) in a region below the first dielectric layer (14) comprises a rectangular shape or a trapezoidal shape or a triangular shape.
  6. The transistor structure (10) according to any one of the preceding claims, further comprising: a first spacer layer (31) arranged between the first auxiliary layer (13-1) and the semiconductor channel layer (12) along the first axis; and/or a second spacer layer (32) arranged between the semiconductor channel layer (12) and the second auxiliary layer (13-2) along the first axis.
  7. The transistor structure (10) according to claim 6, wherein: the first spacer layer (31) and/or the second spacer layer (32) comprise a third material, the third material having a third relative permittivity, and the third relative permittivity being larger than the first relative permittivity and smaller than the second relative permittivity.
  8. The transistor structure (10) according to claim 7, wherein: the third material comprises SiO2.
  9. A vertical NAND flash memory (100, 110) comprising one or more transistor structures (10) according to any one of the preceding claims.
  10. A method (90) for fabricating a transistor structure (10) for a vertical NAND flash memory, the method comprising: forming (91) a semiconductor channel layer (12); forming (92) a first auxiliary layer (13-1) and a second auxiliary layer (13-2) at two opposite sides of the semiconductor channel layer (12) along a first axis, wherein each of the first auxiliary layer (13-1) and the second auxiliary layer (13-2) comprises a first material with a first relative permittivity, the first relative permittivity being larger than 1 and lower than 3.9; forming (93) a first dielectric layer (14) above the semiconductor channel layer (12), the first auxiliary layer (13-1) and the second auxiliary layer (13-2), along a second axis perpendicular to the first axis; forming (94) a charge storage layer (15) on the first dielectric layer (14); forming (95) a second dielectric layer (16) on the charge storage; and forming (96) a gate layer (17) on the second dielectric layer (16).

Description

TECHNICAL FIELD The present disclosure provides a transistor structure for a vertical NAND flash memory, and a method for processing the transistor structure. A vertical NAND flash memory comprising one or more of the transistor structures is also provided. BACKGROUND A flash memory is a type of non-volatile memory that can be electrically programmed and erased. A NAND flash is a special type of flash memory, in which the individual memory cells are connected in series in the form of a NAND gate. A NAND flash with a three-dimensional (3D) architecture, i.e. a NAND flash with memory cells that are arranged vertically, is generally referred to as 3D NAND or vertical NAND. NAND flash memory is able to store information in a non-volatile way in the form of charge carriers (electrons or holes), either in a charge trap layer or in a floating gate that is part of a flash cell transistor. The concentration of stored charge carriers corresponds to the bits of information stored in the memory, and can be read by a resulting threshold voltage shift of the flash cell transistor. Quantum tunneling is utilized to change the concentration of the charge carriers, thereby writing or erasing information to/from the memory. The dimensions of the flash cells of the vertical NAND flash memories have been scaled down over successive technology generations to increase bit densities. The production technology has transitioned from planar devices to vertical, 3D structures, in which the memory string consists of a cylindrical memory hole along which the flash cells are stacked, also called gate-all-around (GAA) strings. These strings can be fabricated by first depositing a stack of alternating layers, followed by etching a memory hole and then filling the memory hole with the memory and channel layers. Such 3D structures allow increasing the bit density by adding more cells to the strings, rather than scaling the cell dimensions. However, the etching process becomes more challenging as the aspect ratio of the memory holes increases, thereby ultimately limiting the number of cells on a string. To further increase the bit density, efforts have focused on scaling down the vertical cell pitch, which comprises the flash cell gate length and the inter-gate spacing. This, however, increases the interference between cells, and degrades the gate control over the carrier injection. Alternatively, a 3D trench cell architecture has been developed for the vertical NAND flash memory. Instead of cylindrical holes, as in the conventional GAA structure, the memory strings in the 3D trench cell architecture are fabricated in elongated trenches, wherein each trench accommodates multiple strings in which the channels are separated with an insulating oxide material. This allows packing the strings very closely together, thereby increasing the bit density. Transitioning to a 3D trench cell with scaled vertical pitch enables large bit densities, but also significantly degrades the memory operation of the cells. The flash cells in the trenches are flat, and therefore do not benefit from the so-called "curvature effect" of GAA cells. In a cylindrical GAA cell, the tunnel oxide has a smaller radius than the blocking oxide, which ensures a larger electric field in the tunnel oxide than in the blocking oxide for a given gate voltage. This benefits the injection of the charge carriers through the tunnel oxide relative to their escape through the blocking oxide, and therefore improves the memory operation. Further, since in the 3D trench cell architecture the memory stack is flat, the electric field is more evenly distributed over the tunnel and blocking oxides. The memory operation the 3D trench cell architecture is further degraded as the vertical cell pitch is scaled, similar to GAA structures. Combined with the flat cell geometry, this can lead to poor overall memory performance. SUMMARY It is thus an objective of this disclosure to provide a 3D trench NAND flash memory structure with improved performance, and an improved method for processing the memory structure. In particular, the above-mentioned disadvantages should be avoided. The objective and other advantages are achieved by the embodiments provided in the independent claims. Advantageous implementations are further defined in the dependent claims. Hereinafter in this disclosure, the terms "vertical NAND flash memory" and "3D trench NAND flash memory structure" are used interchangeably. That is, the disclosure is concerned with a vertical NAND flash memory with the trench structure, and not to a GAA structure. According to a first aspect, the present disclosure relates to a transistor structure for a vertical NAND flash memory device. The transistor structure comprises a semiconductor channel layer, and a first auxiliary layer and a second auxiliary layer arranged at two opposite sides of the semiconductor channel layer along a first axis, wherein each of the first auxiliary layer and the second auxi