EP-4739026-A1 - SINGLE ETCH AND PIER MERGE METHOD FOR CELL AND COMB FEATURES

Abstract

Methods, systems, and devices for single etch and pier merge method for cell and comb features are described. One or more pillars and one or more piers for a memory array may be patterned, aligned, and formed in one processing step. For example, the one or more piers and the one or more pillars may be patterned and etched using a pillar shape to form a set of pillar cavities. A first subset of the pillar cavities may be etched such that pairs of adjacent pillar cavities merge to form a pier cavity that is filled with a first material and a liner to form the one or more piers. A second subset of the pillar cavities may be filled with the liner and the first material to form the one or more pillars. Comb edge structures may be formed based on a third subset of the pillar cavities.

Inventors

• GOOD, FARRELL M.
• Plaisted, Trevor J.

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260506

Application Date

20251105

Claims (8)

1. An apparatus, comprising: a substrate; a stack of materials comprising alternating layers of a first material and a second material; a plurality of piers extending through the stack of materials, wherein each pier of the plurality of piers is positioned above a third material that extends into the substrate; a plurality of pillars extending through the stack of materials, wherein each pillar of the plurality of pillars is positioned above a fourth material that extends into the substrate; and a plurality of comb edge structures extending through the stack of materials, wherein each comb edge structure of the plurality of comb edge structures is positioned above the third material, and wherein a portion of the first material extends, at each layer of the first material in the stack of materials, at least partially into a respective pier, a respective pillar, and a respective comb edge structure.
2. The apparatus of claim 1, wherein the plurality of comb edge structures comprises a first comb edge structure and a second comb edge structure, the plurality of pillars and the plurality of piers positioned between the first comb edge structure and the second comb edge structure.
3. The apparatus of either of claims 1 or 2, wherein the plurality of comb edge structures form a boundary of one or more comb structures, the one or more comb structures corresponding to one or more word lines.
4. The apparatus of any preceding claim, wherein a first pillar and a second pillar of the plurality of pillars are separated by a pier of the plurality of piers.
5. The apparatus of any preceding claim, wherein each of the plurality of pillars comprises the first material and a liner.
6. The apparatus of claim 5, wherein the liner comprises a silicon carbon nitride material.
7. The apparatus of any preceding claim, wherein the first material comprises a nitride material and the second material comprises an oxide material.
8. The apparatus of any preceding claim, wherein the third material comprises an aluminum oxide material or a tungsten material and the fourth material comprises a polysilicon material.

Description

TECHNICAL FIELD The following relates to one or more systems for memory, including single etch and pier merge method for cell and comb features. BACKGROUND Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often denoted by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any one of which may be stored. To access the stored information, the memory device may read (e.g., sense, detect, retrieve, determine) states from the memory cells. To store information, the memory device may write (e.g., program, set, assign) states to the memory cells. Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, not-or (NOR) and not-and (NAND) memory devices, and others. Memory cells may be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration may maintain stored logic states for extended periods of time even in the absence of an external power source. Memory cells configured in a volatile configuration may lose stored states when disconnected from an external power source. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows an example of a memory array that supports a single etch and pier merge method for cell and comb features in accordance with examples as disclosed herein.FIG. 2 shows a top view of an example of a memory array that supports a single etch and pier merge method for cell and comb features in accordance with examples as disclosed herein.FIGs. 3A and 3B show side views of an example of a memory array that supports a single etch and pier merge method for cell and comb features in accordance with examples as disclosed herein.FIGs. 4 through 9 show examples of processing steps of a single etch and pier merge method for cell and comb features in accordance with examples as disclosed herein.FIG. 10 shows examples of cross-sectional views that support single etch and pier merge method for cell and comb features in accordance with examples as disclosed herein.FIGs. 11A and 11B show examples of elevation views that supports a single etch and pier merge method for cell and comb features in accordance with examples as disclosed herein.FIG. 12 shows a flowchart illustrating a method or methods that support single etch and pier merge method for cell and comb features in accordance with examples as disclosed herein. DETAILED DESCRIPTION In some memory architectures, an array of memory cells may be formed by etching a stack of materials multiple times (e.g., at least twice). For example, one or more piers may be patterned and formed in a first processing step that includes a first etching process, and one or more pillars may be patterned and formed in a second processing step that includes a second etching process. The piers may form one or more first access lines (e.g., bit lines) to access memory cells in the array. In such memory architectures, the etching processes may be optimized for circular shapes, resulting in challenges for forming the one or more piers (e.g., which may be generally elliptical shaped) using the first etching process. For example, as the density of memory cells in the array increases, the accuracy of the first etching process along an axis of an elliptical-shaped pier may degrade. That is, methods of forming generally elliptical shaped piers may not scale with higher densities of memory cells. Thus, a method to reliably form generally elliptical shaped piers may be desirable. The techniques described herein enable one or more pillars and one or more piers to be patterned, aligned, and formed in fewer processing steps (e.g., one processing step) relative to conventional methods. For example, the one or more piers and the one or more pillars may be patterned using a pillar shape (e.g., a circular shape) to form a set of pillar cavities. A first subset of the pillar cavities may be etched such that pairs of pillar cavities merge to form a pier cavity that is filled with a first material and a liner to form the one or more piers. A second subset of the pillar cavities may be filled with the liner and the first material to form the one or more pillars. In some examples, a third subset of the pillar cavities may be etched such that two or more pillar cavities merge to form a cavity (e.g., a comb edge structure cavity) that is filled with a third material to form one or more comb edge structures. T