EP-4739027-A2 - UNIFIED SEMICONDUCTOR DEVICES HAVING PROCESSOR AND HETEROGENEOUS MEMORIES AND METHODS FOR FORMING THE SAME

Abstract

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes NAND memory cells and a first bonding layer including first bonding contacts. The semiconductor device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The semiconductor device also includes a third semiconductor structure including a processor, SRAM cells, and a third bonding layer including third bonding contacts. The semiconductor device further includes a first bonding interface between the first and third bonding layers, and a second bonding interface between the second and third bonding layers. The first bonding contacts are in contact with a first set of the third bonding contacts at the first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at the second bonding interface. The first and second bonding interfaces are in a same plane.

Inventors

• CHENG, WEIHUA
• LIU, JUN

Assignees

• Yangtze Memory Technologies Co., Ltd.

Dates

Publication Date

20260506

Application Date

20190911

Claims (15)

1. A semiconductor device 100; 200), comprising: a controller (208; 102) comprising peripheral circuits and an array of static random-access memory, SRAM, cells, wherein the peripheral circuits and an array of SRAM cells are formed in different regions in the same plane; at least one memory die (214) comprising volatile memory cells and electrically connected to the controller; and at least one non-volatile die (212) comprising an array of non-volatile memory cells and electrically connected to the controller; wherein the controller is configured to control operations of the memory die (214) and the non-volatile die (212).
2. The semiconductor device of claim 1, wherein the memory die (214) is stacked on the controller, and the non-volatile die (212) is stacked on the memory die (214).
3. The semiconductor device of claim 1, wherein the memory die (214) is electrically connected to the controller through copper bonding wires.
4. The semiconductor device of claim 1, wherein the non-volatile die (212) is electrically connected to the controller through copper bonding wires.
5. The semiconductor device of claim 1, wherein the controller is configured to control data transfer between the non-volatile memory cells and the volatile memory cells.
6. The semiconductor device of claim 1, wherein the non-volatile die is configured to store a logical-physical address map, and the controller is configured to load the logical-physical address map from the non-volatile memory cells to the volatile memory cells when the semiconductor device is powered on.
7. The semiconductor device of claim 6, wherein the SRAM cells are configured to store a log of updates to the logical-physical address map.
8. The semiconductor device of claim 1, wherein the controller comprises one or more bus interface units configured to receive and transmit data.
9. The semiconductor device of claim 1, further comprising a circuit board (206), wherein the controller is stacked on the circuit board.
10. The semiconductor device of claim 1, wherein the peripheral circuits comprise one or more of an input/output buffer, a row decoder, a column decoder, or a sense amplifier.
11. The semiconductor device of claim 1, wherein the volatile memory cells comprise DRAM memory cells, and the non-volatile memory cells comprise NAND memory cells.
12. The semiconductor device of claim 1, wherein the non-volatile die (212) comprises a plurality of first bonding contacts, the memory die (214) comprises a plurality of second bonding contacts, the controller comprises a plurality of third bonding contacts, and the non-volatile die (212) and the memory die (214) are electrically connected to the controller through the first bonding contacts, the second bonding contacts and the third bonding contacts.
13. The semiconductor device of claim 1, further comprising a processor on a substrate, wherein the SRAM cells are on the substrate and outside of the processor.
14. The semiconductor device of claim 1, wherein the peripheral circuits and the SRAM cells are formed in different regions in the same plane outside of a processor.
15. The semiconductor device of claim 1, further comprising a plurality of non-volatile die (212) stacked with each other.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priorities to International Application No. PCT/CN2019/082607, filed on April 15, 2019, entitled "INTEGRATION OF THREE-DIMENSIONAL NAND MEMORY DEVICES WITH MULTIPLE FUNCTIONAL CHIPS," International Application No. PCT/CN2019/097442, filed on July 24, 2019, entitled "BONDED UNIFIED SEMICONDUCTOR CHIPS AND FABRICATION AND OPERATION METHODS THEREOF," and International Application No. PCT/CN2019/085237, filed on April 30, 2019, entitled "THREE-DIMENSIONAL MEMORY DEVICE WITH EMBEDDED DYNAMIC RANDOM-ACCESS MEMORY," all of which are incorporated herein by reference in their entireties. BACKGROUND Embodiments of the present disclosure relate to semiconductor devices and fabrication methods thereof. In modern mobile devices (e.g., smartphones, tablets, etc.), multiple complicated system-on-chips (SOCs) are used to enable various functionalities, such as application processor, dynamic random-access memory (DRAM), flash memory, various controllers for Bluetooth, Wi-Fi, global positioning system (GPS), frequency modulation (FM) radio, display, etc., and baseband processor, which are formed as discrete chips. For example, application processor typically is large in size including central processing units (CPUs), graphics processing units (GPUs), on-chip memory, accelerating function hardware, and other analog components. SUMMARY Embodiments of semiconductor devices and fabrication methods thereof are disclosed herein. In one example, a semiconductor device includes an array of NAND memory cells and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device also includes a third semiconductor structure including a processor, an array of static random-access memory (SRAM) cells, and a third bonding layer including a plurality of third bonding contacts. The semiconductor device further includes a first bonding interface between the first bonding layer and the third bonding layer, and a second bonding interface between the second bonding layer and the third bonding layer. The first bonding contacts are in contact with a first set of the third bonding contacts at the first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at the second bonding interface. The first bonding interface and the second bonding interface are in a same plane. In another example, a method for forming a semiconductor device is disclosed. A plurality of first semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes an array of NAND memory cells and a first bonding layer including a plurality of first bonding contacts. The first wafer is diced into a plurality of first dies, such that at least one of the first dies includes the at least one of the first semiconductor structures. A plurality of second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. The second wafer is diced into a plurality of second dies, such that at least one of the second dies includes the at least one of the second semiconductor structures. A plurality of third semiconductor structures are formed on a third wafer. At least one of the third semiconductor structures includes a processor, an array of SRAM cells, and a third bonding layer including a plurality of third bonding contacts. The third wafer is diced into a plurality of third dies, such that at least one of the third dies includes the at least one of the third semiconductor structures. The third die and each of the first die and the second die are bonded in a face-to-face manner, such that the third semiconductor structure is bonded to each of the first semiconductor structure and the second semiconductor structure. The first bonding contacts are in contact with a first set of the third bonding contacts at a first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at a second bonding interface. In still another example, a method for forming a semiconductor device is disclosed. A plurality of first semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes an array of NAND memory cells and a first bonding layer including a plurality of first bonding contacts. The first wafer is diced into a plurality of first dies, such that at least one of the first dies includes the at least one of the first semiconductor structures. A plurality of second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structur