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EP-4739029-A1 - SPLIT-GATE MOSFET WITH REDUCED ON RESISTANCE AND REDUCED GATE-DRAIN CAPACITY

EP4739029A1EP 4739029 A1EP4739029 A1EP 4739029A1EP-4739029-A1

Abstract

Electronic device (10), comprising: a semiconductor body (12); trenches (13) in the semiconductor body (12); an insulating field plate region (14) in each trench (13); a conductive gate region (15) in each trench (13), electrically insulated from the semiconductor body (12) by means of the respective insulating field plate region (14); a field plate region (16) in each trench (13); gate interconnections (28) within the semiconductor body (12), lateral to the trenches (13), electrically insulated from the semiconductor body (12) and electrically connected to the conductive gate regions (15) in such a way as to electrically interconnect the conductive gate regions (15) with each other; and body regions (17). The ones of the conductive gate regions (15) and the gate interconnections (28) are part of respective inactive gate structures (22') of the electronic device (10), adapted to locally inhibit the formation of a conduction channel through the body regions (17), and the others of the conductive gate regions (15) and gate interconnections (28) are part of respective active gate structures (22") of the electronic device (10), adapted to locally allow the formation of a conduction channel through the body regions (17).

Inventors

  • ENEA, VINCENZO

Assignees

  • STMicroelectronics International N.V.

Dates

Publication Date
20260506
Application Date
20251010

Claims (15)

  1. An electronic device (10), comprising: a semiconductor body (12), with a first conductivity type (N), having a first and a second side (12a, 12b) opposite to each other along a first axis (Z); a plurality of trenches (13) extending within the semiconductor body (12) from the first side (12a) towards the second side (12b) and terminating within the semiconductor body (12); a respective insulating region (14) in each of said trenches (13), covering the lower and lateral walls of the respective trench (13); a respective conductive gate region (15) in each of said trenches (13) on a respective first portion (14a) of the respective insulating region (14), each conductive gate region (15) being of conductive material and being electrically insulated from the semiconductor body (12) by means of a respective second portion (14b) of the respective insulating region (14); a respective field plate region (16) in each of said trenches (13), each field plate region (16) being buried in the respective first portion (14a) of the respective insulating region (14) and being electrically insulated from the respective conductive gate region (15) and the semiconductor body (12) by means of a respective third portion (14c) of the respective insulating region (14); a plurality of gate interconnections (28) extending within the semiconductor body (12) from the first side (12a) towards the second side (12b), laterally to the trenches (13), and terminating within the semiconductor body (12), the gate interconnections (28) being of conductive material, being electrically insulated from the semiconductor body (12) and being electrically connected to the conductive gate regions (15) in such a way as to electrically interconnect the conductive gate regions (15) with each other; and a plurality of body regions (17) extending at the first side (12a) between the trenches (13), the body regions (17) having a second conductivity type (P) opposite to the first conductivity type (N), being lateral to the gate interconnections (28) and the conductive gate regions (15) and being electrically insulated with respect to the gate interconnections (28) and the conductive gate regions (15), wherein the ones of the conductive gate regions (15) and the gate interconnections (28) are part of respective inactive gate structures (22') of the electronic device (10), configured to locally inhibit the formation of a conduction channel through the body regions (17), and the others of the conductive gate regions (15) and the gate interconnections (28) are part of respective active gate structures (22") of the electronic device (10), configured to locally allow the formation of a conduction channel through the body regions (17).
  2. The electronic device according to claim 1, wherein the ones of the conductive gate regions (15) and the gate interconnections (28) each have a respective first minimum distance (D1) from an interface between the respective body region (17) and the semiconductor body (12) and wherein the others of the conductive gate regions (15) and the gate interconnections (28) each have a respective second minimum distance (D2) from an interface between the respective body region (17) and the semiconductor body (12), the first minimum distance (D1) being greater than the second minimum distance (D2).
  3. The electronic device according to claim 2, wherein the first minimum distance (D1) is equal to at least 50% more than the second minimum distance (D2).
  4. The electronic device according to any of the preceding claims, further comprising a plurality of interconnection trenches (31), each interconnection trench (31) extending within the semiconductor body (12) from the first side (12a) towards the second side (12b) and terminating within the semiconductor body (12), wherein the interconnection trenches (31) are interposed, orthogonally to the first axis (Z), between the trenches (13) and are communicating with the trenches (13), wherein the gate interconnections (28) extend within the interconnection trenches (31) in such a way as to electrically contact the conductive gate regions (15) with each other, the electronic device (10) further comprising insulating interconnection portions (29), of insulating material, which extend in the interconnection trenches (31) in such a way as to be interposed between the gate interconnections (28) and both the semiconductor body (12) and the body regions (17) to electrically insulate the gate interconnections (28) from the body regions (17) and from the semiconductor body (12).
  5. The electronic device according to any of the preceding claims, wherein each insulating region (14) has a respective upper surface of the curved type that defines a respective concavity (54), wherein each conductive gate region (15) extends in the respective concavity (54), wherein each conductive gate region (15) has a first depth (P1), the maximum depth, at a first region of the conductive gate region (15) which orthogonally to the first axis (Z) is radially internal, and has a second depth (P2), the minimum depth, at a second region of the conductive gate region (15) which orthogonally to the first axis (Z) is radially external and surrounds said first radially internal region, the first region and the second region being continuous with each other, the first depth (P1) and the second depth (P2) being measured parallel to the first axis (Z) starting from an upper surface of the conductive gate region (15), the first depth (P1) being greater than the second depth (P2) and the depth of the conductive gate region (15) varying continuously between the first depth (P1) and the second depth (P2).
  6. The electronic device according to any of the preceding claims, wherein, orthogonally to the first axis (Z), the trenches (13) have a closed polygonal shape and a matrix arrangement.
  7. The electronic device according to claim 6, wherein the number of body regions (17) for each trench (13) is equal to the number of sides, in top view, of the closed polygonal shape of the trench (13), such that each body region (17) is associated with a respective side of the trench (13), the electronic device further comprising, for each trench (13), a respective plurality of source regions (20) having the first conductivity type and extending on a respective body region (17) of the body regions (17), the number of source regions (20) for each trench (13) being equal to the number of sides, in top view, of the closed polygonal shape of the trench (13), such that each source region (20) is associated with a respective side of the trench (13), wherein the gate interconnections (28) are physically and electrically connected to the respective conductive gate regions (15), wherein each gate interconnection (28) connects a least one vertex of one of the conductive gate regions (15) to at least one vertex of an adjacent conductive gate region (15) of the conductive gate regions (15) and to another vertex of another adjacent conductive gate region (15) of the conductive gate regions (15).
  8. The electronic device according to claim 6 or 7, wherein one of the following configurations a-c applies: a: the trenches (13) and the conductive gate regions (15) have a hexagonal shape orthogonally to the first axis (Z), wherein each gate interconnection (28) connects to each other three respective gate regions (15) that are first neighboring to each other in the matrix arrangement, wherein each gate interconnection (28) has three respective arms, each arm having a respective first and a respective second end opposite to each other with respect to the direction of main extension of the arm, the first ends of the arms of each gate interconnection (28) being joined to each other to form a joining portion of the gate interconnection (28), starting from which the respective three arms extend radially in such a way as to be angularly equi-spaced from each other orthogonally to the first axis (Z), wherein the second end of each arm of each gate interconnection (28) is coupled to a respective vertex of a respective of the three gate regions (15) that, in the matrix arrangement, surround the respective gate interconnection (28), b: the trenches (13) are aligned with each other, in the matrix arrangement, both along a second axis (X) orthogonal to the first axis (Z) and along a third axis (Y) orthogonal to both the first axis (Z) and the second axis (X), wherein the trenches (13) and the conductive gate regions (15) have a quadrilateral shape, in particular a square shape, orthogonally to the first axis (Z), wherein the gate interconnections (28) are grouped in groups each of four respective gate interconnections (28), each group of gate interconnections (28) connecting to each other four respective gate regions (15) that are first neighboring to each other in the matrix arrangement, wherein each group of gate interconnections (28) forms a conductive path that, orthogonally to the first axis (Z), is of an annular type and has a quadrilateral shape, in particular a square shape, wherein each vertex of the quadrilateral shape of each conductive path is connected to a respective vertex of a respective of the four gate regions (15) that, in the matrix arrangement, surround the respective group of gate interconnections (28), c: the trenches (13), in the matrix arrangement, are aligned with each other along a second axis (X) orthogonal to the first axis (Z) and are aligned with each other alternately along a third axis (Y) orthogonal to both the first axis (Z) and the second axis (X), wherein the trenches (13) and the conductive gate regions (15) have a quadrilateral shape, in particular a square shape, orthogonally to the first axis (Z), wherein the gate interconnections (28) are grouped to form serpentine paths of gate interconnections (28), each serpentine path having a main extension along the direction of the second axis (X) and extending, along the direction of the third axis (Y), between two respective rows of conductive gate regions (15), each row comprising respective conductive gate regions (15) that are aligned with each other along the direction of the second axis (X), each serpentine path being coupled to vertices of the respective conductive gate regions (15) in such a way as to couple to each other, in succession, the conductive gate regions (15) of said two respective rows having the serpentine path interposed therebetween.
  9. The electronic device according to claim 7 or claim 8 when depending on claim 7, further comprising: a gate metallization that is located at the first side (12a) of the semiconductor body (12) and is directly electrically connected to one part of the conductive gate regions (15); a source metallization (24) that is located at the first side (12a) of the semiconductor body (12) and is electrically connected to the source regions (20) and the field plate regions (16); and a drain metallization (26) that is located at the second side (12b) of the semiconductor body (12).
  10. The electronic device according to claim 9, wherein the source metallization (24) has a respective metallization portion (24c) for each trench (13), each metallization portion (24c) extending through the respective conductive gate region (15) along the direction of the first axis (Z) up to reaching the respective field plate region (16), wherein each metallization portion (24c) is electrically insulated with respect to the respective conductive gate region (15) through the respective third portion (14c) of the insulating region (14) which, orthogonally to the first axis (Z), has annular shape, surrounds the respective metallization portion (24c) and has a width greater than a minimum width equal to 50 nm.
  11. The electronic device according to any of the preceding claims, being of the vertical conduction type.
  12. A process for manufacturing an electronic device (10), comprising the steps of: forming a plurality of trenches (13) within a semiconductor body (12), the semiconductor body (12) having a first and a second side (12a, 12b) opposite to each other along a first axis (Z), the trenches (13) extending from the first side (12a) towards the second side (12b) and terminating within the semiconductor body (12); forming a respective insulating region (14) in each of said trenches (13), covering the lower and lateral walls of the respective trench (13); forming a respective field plate region (16) in each of said trenches (13), each field plate region (16) being buried in a respective first portion (14a) of the respective insulating region (14) and being electrically insulated from the semiconductor body (12) by means of a respective third portion (14c) of the respective insulating region (14); forming a respective conductive gate region (15) in each of said trenches (13) on the respective first portion (14a) of the respective insulating region (14), each conductive gate region (15) being of conductive material and being electrically insulated from the semiconductor body (12) and the respective field plate region (16) by means of a respective second portion (14b) of the respective insulating region (14); forming a plurality of gate interconnections (28) extending within the semiconductor body (12) from the first side (12a) towards the second side (12b), laterally to the trenches (13), and terminating within the semiconductor body (12), the gate interconnections (28) being of conductive material, being electrically insulated from the semiconductor body (12) and being electrically connected to the conductive gate regions (15) in such a way as to electrically interconnect the conductive gate regions (15) with each other; and forming a plurality of body regions (17) extending at the first side (12a) between the trenches (13), the body regions (17) having a second conductivity type (P) opposite to the first conductivity type (N), being lateral to the gate interconnections (28) and the conductive gate regions (15) and being electrically insulated with respect to the gate interconnections (28) and the conductive gate regions (15), wherein the ones of the conductive gate regions (15) and the gate interconnections (28) are part of respective inactive gate structures (22') of the electronic device (10), configured to locally inhibit the formation of a conduction channel through the body regions (17), and the others of the conductive gate regions (15) and the gate interconnections (28) are part of respective active gate structures (22") of the electronic device (10), configured to locally allow the formation of a conduction channel through the body regions (17) .
  13. The manufacturing process according to claim 12, further comprising, after the step of forming the field plate regions (16), the steps of: partially etching a respective insulating filling region (51) in each trench (13) at the first side (12a), to form a recess (54) in each trench (13) and define a main body (14a) of each insulating region (14); selectively removing portions of the semiconductor body (12) starting from the first side (12a) to form interconnection trenches (31), each interconnection trench (31) extending within the semiconductor body (12) from the first side (12a) towards the second side (12b) and terminating within the semiconductor body (12), the interconnection trenches (31) being interposed, orthogonally to the first axis (Z), between the trenches (13) and being communicating with the trenches (13); and forming an insulating layer (57) in the interconnection trenches (31) and the recesses (54), the portions of the insulating layer (57) present in the interconnection trenches (31) defining insulating interconnection portions (29) that extend in the interconnection trenches (31), and wherein the step of forming the conductive gate regions (15) and the step of forming the gate interconnections (28) are performed simultaneously by depositing conductive material in the recesses (54) and in the interconnection trenches (31), respectively, such that the insulating interconnection portions (29) are interposed between the gate interconnections (28) and the semiconductor body (12) in the interconnection trenches (31).
  14. The manufacturing process according to claim 12, further comprising, after the step of forming the field plate regions (16), the steps of: partially etching a respective insulating filling region (51) in each trench (13) at the first side (12a), to form a recess (54) in each trench (13); forming a first intermediate insulating layer (70) in the recesses (54) and on the exposed regions of the semiconductor body (12); selectively removing portions of the semiconductor body (12) starting from the first side (12a) to form interconnection trenches (31), each interconnection trench (31) extending within the semiconductor body (12) from the first side (12a) towards the second side (12b) and terminating within the semiconductor body (12), the interconnection trenches (31) being interposed, orthogonally to the first axis (Z), between the trenches (13) and being communicating with the trenches (13); selectively removing parts of the first intermediate insulating layer (70), leaving the portions of the first intermediate insulating layer (70) that extend on lateral walls of the field plate regions (16) and on the lateral walls of the trenches (13); forming a second intermediate insulating layer (72) on the recessed portions of the insulating filling region (51), on exposed regions of the semiconductor body (12) and field plate regions (16), and on the remaining portions of the first intermediate insulating layer (70); selectively removing part of the second intermediate insulating layer (72) to put in direct communication the recesses (54) and the interconnection trenches (31); and forming an insulating layer (57) in the interconnection trenches (31) and the recesses (54), the portions of the insulating layer (57) present in the interconnection trenches (31) defining insulating interconnection portions (29) that extend in the interconnection trenches (31), and wherein the step of forming the conductive gate regions (15) and the step of forming the gate interconnections (28) are performed simultaneously by depositing conductive material in the recesses (54) and in the interconnection trenches (31), respectively, such that the insulating interconnection portions (29) are interposed between the gate interconnections (28) and the semiconductor body (12) in the interconnection trenches (31).
  15. The manufacturing process according to claim 13 or 14, wherein, if the conductive gate regions (15) are part of the inactive gate structures (22') and the gate interconnections (28) are part of the active gate structures (22"), the gate interconnections (28) each have a respective lower surface at a depth with respect to the first side (12a) and along the first axis (Z) that is greater than a depth with respect to the first side (12a) and along the first axis (Z) of an interface between the respective body region (17) and the semiconductor body (12), and the conductive gate regions (15) each have a respective lower surface at a minimum depth with respect to the first side (12a) and along the first axis (Z) that is lower than a depth with respect to the first side (12a) and along the first axis (Z) of an interface between the respective body region (17) and the semiconductor body (12), or wherein, if the gate interconnections (28) are part of the inactive gate structures (22') and the conductive gate regions (15) are part of the active gate structures (22"), the gate interconnections (28) each have a respective lower surface at a depth with respect to the first side (12a) and along the first axis (Z) that is lower than a depth with respect to the first side (12a) and along the first axis (Z) of an interface between the respective body region (17) and the semiconductor body (12), and the conductive gate regions (15) each have a respective lower surface at a minimum depth with respect to the first side (12a) and along the first axis (Z) that is greater than a depth with respect to the first side (12a) and along the first axis (Z) of an interface between the respective body region (17) and the semiconductor body (12).

Description

TECHNICAL FIELD The present invention relates to a split-gate MOSFET with reduced on-resistance and reduced gate-drain capacity, in particular to an electronic device with gate interconnections that increase the channel perimeter and the conduction area and with a locally selectively inactivated conduction channel. Furthermore, it relates to a manufacturing process of the electronic device. BACKGROUND MOSFET ("Metal-Oxide-Semiconductor Field-Effect Transistor") technology is now widely recognized as an excellent option for several applications, for example for switches in power supply management circuits. Commercially available now for decades, vertical diffused MOSFET (VDMOS) devices have seen significant commercial spread by virtue of their improved electrical performances. However, for a long time, VDMOSFETs have had a high on-state resistance that limited their current handling capabilities. This problem has been overcome with "trench-gate" MOSFETs. By virtue of the vertical-direction channel, these devices allow a reduction in cell pitch without negatively affecting current spread. In particular, the introduction of devices that use a field plate, insulated from the gate electrode and connected to the source potential, as an extension of the gate electrode has enabled the lateral depletion of the off-state drift region. Since the field plate is electrically insulated from the gate electrode, this structure is also known as "shielded-gate" or "split-gate" structure. Split-gate technology offers significant advantages with respect to previous MOSFETs, for example an improved on-resistance with respect to the active area extension and reduced gate-drain capacity. In fact, the split-gate structure allows the use of high doping concentrations, leading to significant improvements in MOSFET performances. As is known, one of the main goals in the development of split-gate power MOSFET devices is the reduction of the on-resistance. This may be achieved in the prior art by reducing the main resistive contributions and/or by increasing the ratio between the conduction area and the channel perimeter with respect to the total area of the device. However, since in the known solutions the elementary cell has a strip shape, the main limitation to achieve these objectives according to the known solutions is the reduction of the dimensions of the elementary cell of the MOSFET, which implies the need to resize the diffusion process and to increase the lithographic resolution to reduce the transversal dimension of the strip. As is evident, this implies significant additional costs and difficulties during the manufacturing step. Furthermore, a further significant issue is that, as the channel perimeter and area increase, if on the one hand the on-resistance is reduced, on the other hand there is an increase in the gate-drain capacity, i.e. the capacity Crss (or Miller capacity Cmiller), and therefore an increase in the amount of gate charge Qg. This entails longer switching times, power and efficiency losses and consequently has a negative impact on the figure of merit (FOM=Rsil*Qg or FOM=Ron*Qg), because the greater gate charge Qg would partly compensate for the benefit resulting from the reduction of the on-resistance. In other words, there is currently a trade-off between the reduction of the on-resistance through the increase of the channel perimeter and the reduction of the gate-drain capacity. This trade-off is a design constraint that complicates the design and limits the final performances of the MOSFET. The aim of the present invention is to provide an electronic device and a manufacturing process of the electronic device which overcome the drawbacks of the prior art and which in particular achieve a significant increase in the conduction area without a corresponding increase in the channel perimeter and the related drain-gate capacity. SUMMARY According to the present invention, an electronic device and a manufacturing process of the electronic device are provided, as defined in the annexed claims which form an integral part of the present description. BRIEF DESCRIPTION OF THE DRAWINGS For a better understanding of the present invention, a preferred embodiment is now described, purely by way of non-limiting example, with reference to the attached drawings, wherein: Figure 1 shows a schematic perspective view along two different section lines of an electronic device, according to one embodiment;Figures 2A and 2B show cross-section views of details of the electronic device of Figure 1;Figures 3A-3C show top views of the electronic device of Figure 1, according to respective embodiments;Figures 4A-4M show schematic perspective views along two different section lines of steps of one embodiment of a manufacturing process of the electronic device of Figure 1;Figures 5A-5H show schematic perspective views along two different section lines of steps of a different embodiment of the manufacturing process of the electronic