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EP-4739030-A1 - SPLIT-GATE MOSFET WITH REDUCED ON RESISTANCE

EP4739030A1EP 4739030 A1EP4739030 A1EP 4739030A1EP-4739030-A1

Abstract

Electronic device (10), comprising: a semiconductor body (12); trenches (13) within the semiconductor body (12) from a first side (12a) towards a second side (12b) of the semiconductor body (12) and terminating within the semiconductor body (12); an insulating field plate region (14) in each of said trenches (13); a conductive gate region (15) in each of said trenches (13) on the respective insulating field plate region (14), each being electrically insulated from the semiconductor body (12) by means of the respective insulating field plate region (14); a field plate region (16) in each of said trenches (13), buried in the respective insulating field plate region (14) and electrically insulated from the respective conductive gate region (15) and from the semiconductor body (12); gate interconnections (28) within the semiconductor body (12), from the first side (12a) towards the second side (12b), lateral to the trenches (13) and terminating in the semiconductor body (12), the gate interconnections (28) being of conductive material, insulated from the semiconductor body (12) and electrically connected to the conductive gate regions (15) in such a way as to electrically interconnect the conductive gate regions (15) with each other.

Inventors

  • ENEA, VINCENZO

Assignees

  • STMicroelectronics International N.V.

Dates

Publication Date
20260506
Application Date
20251010

Claims (15)

  1. An electronic device (10), comprising: a semiconductor body (12) having a first and a second side (12a, 12b) opposite to each other along a first axis (Z); a plurality of trenches (13) extending within the semiconductor body (12) from the first side (12a) towards the second side (12b) and terminating within the semiconductor body (12); a respective insulating region (14) in each of said trenches (13), covering the lower and lateral walls of the respective trench (13); a respective conductive gate region (15) in each of said trenches (13) on a respective first portion (14a) of the respective insulating region (14), each conductive gate region (15) being of conductive material and being electrically insulated from the semiconductor body (12) by means of a respective second portion (14b) of the respective insulating region (14); a respective field plate region (16) in each of said trenches (13), each field plate region (16) being buried in the respective first portion (14a) of the respective insulating region (14) and being electrically insulated from the respective conductive gate region (15) and the semiconductor body (12) by means of a respective third portion (14c) of the respective insulating region (14); a plurality of gate interconnections (28) extending within the semiconductor body (12) from the first side (12a) towards the second side (12b), laterally to the trenches (13), and terminating within the semiconductor body (12), the gate interconnections (28) being of conductive material, being electrically insulated from the semiconductor body (12) and being electrically connected to the conductive gate regions (15) in such a way as to electrically interconnect the conductive gate regions (15) with each other.
  2. The electronic device according to claim 1, further comprising a plurality of interconnection trenches (31), each interconnection trench (31) extending within the semiconductor body (12) from the first side (12a) towards the second side (12b) and terminating within the semiconductor body (12), wherein the interconnection trenches (31) are interposed, orthogonally to the first axis (Z), between the trenches (13) and are communicating with the trenches (13), wherein the gate interconnections (28) extend within the interconnection trenches (31) in such a way as to electrically contact the conductive gate regions (15) with each other, the electronic device (10) further comprising insulating interconnection portions (29), of insulating material, which extend in the interconnection trenches (31) in such a way as to be interposed between the gate interconnections (28) and the semiconductor body (12) to electrically insulate the gate interconnections (28) from the semiconductor body (12).
  3. The electronic device according to claim 1 o 2, wherein, orthogonally to the first axis (Z), the trenches (13) have a closed polygonal shape and a matrix arrangement.
  4. The electronic device according to claim 3, wherein the trenches (13) and the conductive gate regions (15) have a hexagonal shape orthogonally to the first axis (Z), wherein each gate interconnection (28) connects to each other three respective gate regions (15) that are first neighboring to each other in the matrix arrangement, wherein each gate interconnection (28) has three respective arms, each arm having a respective first and a respective second end opposite to each other with respect to the direction of main extension of the arm, the first ends of the arms of each gate interconnection (28) being joined to each other to form a joining portion of the gate interconnection (28), starting from which the respective three arms extend radially in such a way as to be angularly equi-spaced from each other orthogonally to the first axis (Z), wherein the second end of each arm of each gate interconnection (28) is coupled to a respective vertex of a respective one of the three gate regions (15) that, in the matrix arrangement, surround the respective gate interconnection (28).
  5. The electronic device according to claim 3, wherein the trenches (13) are aligned with each other, in the matrix arrangement, both along a second axis (X) orthogonal to the first axis (Z) and along a third axis (Y) orthogonal to both the first axis (Z) and the second axis (X), wherein the trenches (13) and the conductive gate regions (15) have a quadrilateral shape, in particular a square shape, orthogonally to the first axis (Z), wherein the gate interconnections (28) are grouped in groups each of four respective gate interconnections (28), each group of gate interconnections (28) connecting to each other four respective gate regions (15) that are first neighboring to each other in the matrix arrangement, wherein each group of gate interconnections (28) forms a conductive path that, orthogonally to the first axis (Z), is of an annular type and has a quadrilateral shape, in particular a square shape, wherein each vertex of the quadrilateral shape of each conductive path is connected to a respective vertex of a respective one of the four gate regions (15) that, in the matrix arrangement, surround the respective group of gate interconnections (28).
  6. The electronic device according to claim 3, wherein the trenches (13), in the matrix arrangement, are aligned with each other along a second axis (X) orthogonal to the first axis (Z) and are aligned with each other alternately along a third axis (Y) orthogonal to both the first axis (Z) and the second axis (X), wherein the trenches (13) and the conductive gate regions (15) have a quadrilateral shape, in particular a square shape, orthogonally to the first axis (Z), wherein the gate interconnections (28) are grouped to form serpentine paths of gate interconnections (28), each serpentine path having a main extension along the direction of the second axis (X) and extending, along the direction of the third axis (Y), between two respective rows of conductive gate regions (15), each row comprising respective conductive gate regions (15) that are aligned with each other along the direction of the second axis (X), each serpentine path being coupled to vertices of the respective conductive gate regions (15) in such a way as to couple to each other, in succession, the conductive gate regions (15) of said two respective rows having the serpentine path interposed therebetween.
  7. The electronic device according to any of the preceding claims, further comprising a gate metallization that is located at the first side (12a) of the semiconductor body (12) and is directly electrically connected to one part of the conductive gate regions (15).
  8. The electronic device according to any of the preceding claims, wherein the semiconductor body (12) has a first conductivity type (N), the electronic device further comprising: a plurality of body regions (17) extending at the first side (12a) between the trenches (13), the body regions (17) having a second conductivity type (P) opposite to the first conductivity type (N); a plurality of source regions (20), each in a respective one of the body regions (17); a source metallization (24) that is located at the first side (12a) of the semiconductor body (12) and is electrically connected to the source regions (20) and the field plate regions (16); and a drain metallization (26) that is located at the second side (12b) of the semiconductor body (12).
  9. The electronic device according to claims 3 and 8, wherein the number of body regions (17) and of the respective source regions (20) for each trench (13) is equal to the number of sides, in top view, of the closed polygonal shape of the trench (13), such that each body region (17) is associated with a respective side of the trench (13), wherein the gate interconnections (28) are physically and electrically connected to the respective conductive gate regions (15), wherein each gate interconnection (28) connects a least one vertex of one of the conductive gate regions (15) to at least one vertex of an adjacent conductive gate region (15) of the conductive gate regions (15) and to another vertex of another adjacent conductive gate region (15) of the conductive gate regions (15).
  10. The electronic device according to claim 8 or 9, wherein the source metallization (24) has a respective metallization portion (24c) for each trench (13), each metallization portion (24c) extending through the respective conductive gate region (15) along the direction of the first axis (Z) up to reaching the respective field plate region (16), wherein each metallization portion (24c) is electrically insulated with respect to the respective conductive gate region (15) through a respective insulation portion (18b), of insulating material, wherein, orthogonally to the first axis (Z), each insulation portion (18b) has an annular shape, surrounds the respective metallization portion (24c) and is interposed between the respective metallization portion (24c) and the respective conductive gate region (15) in such a way as to space, orthogonally to the first axis (Z), the respective metallization portion (24c) and the respective conductive gate region (15) by at least a minimum distance equal to 50 nm.
  11. The electronic device according to any of the preceding claims, being of the vertical conduction type.
  12. A process for manufacturing an electronic device (10), comprising the steps of: forming a plurality of trenches (13) within a semiconductor body (12), the semiconductor body (12) having a first and a second side (12a, 12b) opposite to each other along a first axis (Z), the trenches (13) extending from the first side (12a) towards the second side (12b) and terminating within the semiconductor body (12); forming a respective insulating region (14) in each of said trenches (13), covering the lower and lateral walls of the respective trench (13); forming a respective field plate region (16) in each of said trenches (13), each field plate region (16) being buried in a respective first portion (14a) of the respective insulating region (14) and being electrically insulated from the semiconductor body (12) by means of a respective third portion (14c) of the respective insulating region (14); forming a respective conductive gate region (15) in each of said trenches (13) on the respective first portion (14a) of the respective insulating region (14), each conductive gate region (15) being of conductive material and being electrically insulated from the semiconductor body (12) and the respective field plate region (16) by means of a respective second portion (14b) of the respective insulating region (14); forming a plurality of gate interconnections (28) extending within the semiconductor body (12) from the first side (12a) towards the second side (12b), laterally to the trenches (13), and terminating within the semiconductor body (12), the gate interconnections (28) being of conductive material, being electrically insulated from the semiconductor body (12) and being electrically connected to the conductive gate regions (15) in such a way as to electrically interconnect the conductive gate regions (15) with each other.
  13. The manufacturing process according to claim 12, further comprising, after the step of forming the field plate regions (16), the steps of: partially etching a respective insulating filling region (51) in each trench (13) at the first side (12a), to form a recess (54) in each trench (13) and define a main body (14a) of each insulating region (14); selectively removing portions of the semiconductor body (12) starting from the first side (12a) to form interconnection trenches (31), each interconnection trench (31) extending within the semiconductor body (12) from the first side (12a) towards the second side (12b) and terminating within the semiconductor body (12), the interconnection trenches (31) being interposed, orthogonally to the first axis (Z), between the trenches (13) and being communicating with the trenches (13); and forming an insulating layer (57) in the interconnection trenches (31) and the recesses (54), the portions of the insulating layer (57) present in the interconnection trenches (31) defining insulating interconnection portions (29) that extend in the interconnection trenches (31), and wherein the step of forming the conductive gate regions (15) and the step of forming the gate interconnections (28) are performed simultaneously by depositing conductive material in the recesses (54) and in the interconnection trenches (31), respectively, such that the insulating interconnection portions (29) are interposed between the gate interconnections (28) and the semiconductor body (12) in the interconnection trenches (31).
  14. The manufacturing process according to claim 12, further comprising, after the step of forming the field plate regions (16), the steps of: partially removing a respective insulating filling region (51) in each trench (13) at the first side (12a), to form a first recess (54) in each trench (13), the field plate regions (16) protruding partly into said first recesses (54); forming a second insulating filling region (60) in the trenches (13) at the first side (12a); partially removing the second insulating filling region (60) at the first side (12a), to form a second recess (61) in each trench (13) such as to leave the field plate regions (16) covered; selectively removing portions of the semiconductor body (12) starting from the first side (12a) to form interconnection trenches (31), each interconnection trench (31) extending within the semiconductor body (12) from the first side (12a) towards the second side (12b) and terminating within the semiconductor body (12), the interconnection trenches (31) being interposed, orthogonally to the first axis (Z), between the trenches (13) and being communicating with the trenches (13); forming an insulating layer (57) in the interconnection trenches (31) and the second recesses (61), the portions of the insulating layer (57) present in the interconnection trenches (31) defining insulating interconnection portions (29) that extend in the interconnection trenches (31), and wherein the step of forming the conductive gate regions (15) and the step of forming the gate interconnections (28) are performed simultaneously by depositing conductive material in the second recesses (61) and in the interconnection trenches (31), respectively, such that the insulating interconnection portions (29) are interposed between the gate interconnections (28) and the semiconductor body (12) in the interconnection trenches (31).
  15. The manufacturing process according to claim 14, further comprising, after the step of forming the conductive gate regions (15) and the step of forming the gate interconnections (28), the steps of: forming an upper oxide layer (63) on the gate regions (15) and on the gate interconnections (28); partially removing the upper oxide layer (63) to form through openings (18') that extend through the upper oxide layer (63) up to the conductive gate regions (15) and are aligned along the direction of the first axis (Z) with the field plate regions (16); forming first field plate contact trenches (65) through the through openings (18'), the first field plate contact trenches (65) extending through the gate regions (15) and the second insulating filling regions (60) up to exposing the field plate regions (16); depositing an oxide layer in the first field plate contact trenches (65), the oxide layer comprising portions present on the field plate regions (16), and insulation portions (18b) which, orthogonally to the first axis (Z), have annular shape and each cover a wall of the respective gate region (15) where exposed by the respective first field plate contact trench (65); forming second field plate contact trenches (67) through the first field plate contact trenches (65), the second field plate contact trenches (67) extending through the oxide layer portions present on the field plate regions (16) up to exposing the field plate regions (16); and forming a source metallization (24) with metallization portions (24c) that extend in the field plate contact trenches (67) in such a way as to be in contact with the field plate regions (16), wherein each metallization portion (24c) is electrically insulated with respect to the respective conductive gate region (15) through the respective insulation portion (18b), of insulating material, and wherein, orthogonally to the first axis (Z), each insulation portion (18b) surrounds the respective metallization portion (24c) and is interposed between the respective metallization portion (24c) and the respective conductive gate region (15) in such a way as to space, orthogonally to the first axis (Z), the respective metallization portion (24c) and the respective conductive gate region (15) by at least a minimum distance equal to 50 nm.

Description

TECHNICAL FIELD The present invention relates to a split-gate MOSFET with reduced on-resistance, in particular to an electronic device with gate interconnections that increase the channel perimeter and the conduction area without the need for resizing the manufacturing process or for high lithographic resolution. Furthermore, it relates to a manufacturing process of the electronic device. BACKGROUND MOSFET ("Metal-Oxide-Semiconductor Field-Effect Transistor") technology is now widely recognized as an excellent option for several applications, for example for switches in power supply management circuits. Commercially available now for decades, vertical diffused MOSFET (VDMOS) devices have seen significant commercial spread by virtue of their improved electrical performances. However, for a long time, VDMOSFETs have had a high on-state resistance that limited their current handling capabilities. This problem has been overcome with "trench-gate" MOSFETs. By virtue of the vertical-direction channel, these devices allow a reduction in cell pitch without negatively affecting current spread. In particular, the introduction of devices that use a field plate, insulated from the gate electrode and connected to the source potential, as an extension of the gate electrode has enabled the lateral depletion of the off-state drift region. Since the field plate is electrically insulated from the gate electrode, this structure is also known as "shielded-gate" or "split-gate" structure. Split-gate technology offers significant advantages with respect to previous MOSFETs, for example an improved on-resistance with respect to the active area extension and reduced gate-drain capacity. In fact, the split-gate structure allows the use of high doping concentrations, leading to significant improvements in MOSFET performances. As is known, one of the main goals in the development of split-gate power MOSFET devices is the reduction of the on-resistance. This may be achieved in the prior art by reducing the main resistive contributions and/or by increasing the ratio between the conduction area and the channel perimeter with respect to the total area of the device. However, since in the known solutions the elementary cell has a strip shape, the main limitation to achieve these objectives according to the known solutions is the reduction of the dimensions of the elementary cell of the MOSFET, which implies the need to resize the diffusion process and to increase the lithographic resolution to reduce the transversal dimension of the strip. As is evident, this implies significant additional costs and difficulties during the manufacturing step. The aim of the present invention is to provide an electronic device and a manufacturing process of the electronic device which overcome the drawbacks of the prior art and which in particular achieve a significant increase in channel perimeter and conduction area without any need for resizing the process or high lithographic resolution. SUMMARY According to the present invention, an electronic device and a manufacturing process of the electronic device are provided, as defined in the annexed claims which form an integral part of the present description. BRIEF DESCRIPTION OF THE DRAWINGS For a better understanding of the present invention, a preferred embodiment is now described, purely by way of non-limiting example, with reference to the attached drawings, wherein: Figure 1 shows a schematic perspective view along two different section lines of an electronic device, according to one embodiment;Figures 2A-2C show top views of the electronic device of Figure 1, according to respective embodiments;Figure 3 shows a schematic perspective view along two different section lines of the present electronic device, according to a different embodiment;Figures 4A-4M show schematic perspective views along two different section lines of manufacturing steps of the electronic device of Figure 1, according to one embodiment; andFigures 5A-5S show schematic perspective views along two different section lines of manufacturing steps of the electronic device of Figure 3, according to a different embodiment. In particular, the Figures are shown with reference to a triaxial Cartesian system defined by an X axis, a Y axis and a Z axis, orthogonal to each other. In the following description, elements common to the different embodiments have been indicated with the same reference numbers. DETAILED DESCRIPTION OF THE INVENTION Figure 1 shows an electronic device 10, in detail a power MOSFET. In particular, the electronic device 10 is of the "split-gate" type, also called "shielded-gate" type. The electronic device 10 is hereinafter more simply also referred to as MOSFET 10. The MOSFET 10 is shown in Figure 1 in cross-section view along two different section lines. In detail, the left section in Figure 1 is taken along the section line A-A shown in Figure 2A, while the right section in Figure 1 is taken along the section line B-