EP-4739031-A1 - SEMICONDUCTOR DEVICE

Abstract

The semiconductor device includes a substrate including an NMOS region and a PMOS region, a first transistor in the NMOS region, including a first gate stack and a first source/drain region adjacent to the first gate stack, and a second transistor in the PMOS region, including a second gate stack and a second source/drain region adjacent to the second gate stack. The first gate stack includes a first high dielectric constant insulating film, an insertion layer, a first metal layer and a first protection layer that are sequentially stacked. The second gate stack includes a second high dielectric constant insulating film, a second metal layer and a second protection layer that are sequentially stacked. An oxygen concentration of the first protection layer is higher than an oxygen concentration of the first metal layer, and an oxygen concentration of the second protection layer is higher than an oxygen concentration of the second metal layer.

Inventors

• AHN, Deok Lae
• SONG, Hee Chan
• LEE, DONG SOO
• KIM, TAEK JUNG
• PARK, SANG HUN

Assignees

• Samsung Electronics Co., Ltd.

Dates

Publication Date

20260506

Application Date

20250909

Claims (13)

1. A semiconductor device comprising: a substrate (100) including an NMOS region (RN) and a PMOS region (RP); a first transistor in the NMOS region (RN), including a first gate stack (G1) and a first source/drain region (105), wherein the first source/drain region (105) is adjacent to at least one side of the first gate stack (G1); and a second transistor in the PMOS region (RP), including a second gate stack (G2) and a second source/drain region (107), wherein the second source/drain region (107) is adjacent to at least one side of the second gate stack (G2), wherein the first gate stack (G1) includes a first high dielectric constant insulating film (131), an insertion layer (210), a first metal layer (141) and a first protection layer (151) that are sequentially stacked in a first direction (DR3), the second gate stack (G1) includes a second high dielectric constant insulating film (132), a second metal layer (142) and a second protection layer (152) that are sequentially stacked in the first direction (D3), an oxygen concentration of the first protection layer (151) is higher than an oxygen concentration of the first metal layer (141), and an oxygen concentration of the second protection layer (152) is higher than an oxygen concentration of the second metal layer (142).
2. The semiconductor device of claim 1, wherein a thickness (T1) of the first protection layer (151) is smaller than a thickness (T2) of the first metal layer (141) in the first direction (D3), and a thickness (T4) of the second protection layer (152) is smaller than a thickness (T5) of the second metal layer (142) in the first direction (D3).
3. The semiconductor device of claim 1 or 2, wherein a thickness (T1) of the first protection layer (151) is equivalent to a thickness (T4) of the second protection layer (152) in the first direction (D3), and a thickness (T2) of the first metal layer (141) is equivalent to a thickness (T5) of the second metal layer (142) in the first direction (D3).
4. The semiconductor device of any preceding claim, wherein a thickness (T3) of the first high dielectric constant insulating film (131) is smaller than a thickness (T6) of the second high dielectric constant insulating film (132) in the first direction (D3).
5. The semiconductor device of any preceding claim, wherein the first protection layer (151) comprises an oxide or an oxynitride of a first element, wherein the first element is the same as an element of the first metal layer (141), and the second protection layer (152) comprises an oxide or an oxynitride of a second element, wherein the second element is the same as an element of the second metal layer (142).
6. The semiconductor device of any preceding claim, wherein a lanthanum (La) concentration in the second high dielectric constant insulating film (132) is higher than a lanthanum (La) concentration in the first high dielectric constant insulating film (131) or wherein a lanthanum (La) concentration in the first high dielectric constant insulating film (131) is higher than a lanthanum (La) concentration in the second high dielectric constant insulating film (132).
7. The semiconductor device of any preceding claim, wherein a thickness (H1) of the first gate stack (G1) is greater than a thickness (H2) of the second gate stack (G2) in the first direction (D3).
8. The semiconductor device of any preceding claim, wherein the first metal layer (141) and the second metal layer (142) respectively comprise at least one of titanium (Ti), aluminum (Al), tungsten (W), molybdenum (Mo) or lanthanum (La).
9. The semiconductor device of any preceding claim, wherein the first metal layer (141) and the second metal layer (142) comprise the same metal material.
10. The semiconductor device of any preceding claim, wherein the substrate (100) includes a cell array region (R1) and a peripheral region (R2), wherein the cell array region (R1) includes a buried gate structure (114), and wherein the peripheral region (R2) includes the NMOS region (RN) and the PMOS region (RP).
11. The semiconductor device of any preceding claim, wherein the first transistor further includes a first gate spacer (181) on at least one side of the first gate stack (G1), and the second transistor further includes a second gate spacer (182) on at least one side of the second gate stack (G2).
12. The semiconductor device of any preceding claim, wherein the insertion layer (210) contains lanthanum (La).
13. The semiconductor device of any preceding claim, wherein the first high dielectric constant insulating film (131) does not contain lanthanum (La), and the second high dielectric constant insulating film (132) contains lanthanum (La).

Description

TECHNICAL FIELD The present disclosure relates to a semiconductor device. BACKGROUND A semiconductor device such as a dynamic random access memory (DRAM) may include a cell array region and a peripheral region (i.e., a core-peri region). In particular, the peripheral region or the core-peri region may include a region in which a PMOS transistor is formed and a region in which an NMOS transistor is formed. Gate structures having different structures are disposed in the region in which the PMOS transistor is formed and the region in which the NMOS transistor is formed. BRIEF SUMMARY The inventive concept of the present disclosure provides a semiconductor device capable of improving device performance and reliability. The inventive concept of the present disclosure is not limited to the problems mentioned above and other problems to be solved by the technical idea of the present disclosure, which are not mentioned herein, will be clearly understood by those skilled in the art from the following description of the present disclosure. According to an aspect of the present disclosure, there is provided a semiconductor device including, a substrate including an NMOS region and a PMOS region, a first transistor in the NMOS region, including a first gate stack and a first source/drain region, where the first source/drain region is adjacent to at least one side of the first gate stack, and a second transistor in the PMOS region, including a second gate stack and a second source/drain region, where the second source/drain region is adjacent to at least one side of the second gate stack, where the first gate stack includes a first high dielectric constant insulating film, an insertion layer, a first metal layer and a first protection layer that are sequentially stacked in a first direction, the second gate stack includes a second high dielectric constant insulating film, a second metal layer and a second protection layer that are sequentially stacked in the first direction, an oxygen concentration of the first protection layer is higher than an oxygen concentration of the first metal layer, and an oxygen concentration of the second protection layer is higher than an oxygen concentration of the second metal layer. According to an aspect of the present disclosure, there is provided a semiconductor device including, a substrate including a cell array region and a peripheral region, where the cell array region includes a buried gate structure and the peripheral region includes an NMOS region and a PMOS region with different conductivity types, a first transistor in the NMOS region, including a first gate stack and a first source/drain region, where the first source/drain region is adjacent to at least one side of the first gate stack, and a second transistor in the PMOS region, including a second gate stack and a second source/drain region, where the second source/drain region is adjacent to at least one side of the second gate stack, where the first gate stack includes a first high dielectric constant insulating film, an insertion layer, a first metal layer and a first protection layer that are sequentially stacked in a first direction, the second gate stack includes a second high dielectric constant insulating film, a second metal layer and a second protection layer that are sequentially stacked in the first direction, an oxygen concentration of the first protection layer is higher than an oxygen concentration of the first metal layer, and an oxygen concentration of the second protection layer is higher than an oxygen concentration of the second metal layer. According to an aspect of the present disclosure, there is provided a semiconductor device including, a substrate including an NMOS region and a PMOS region, a first transistor in the NMOS region, including a first gate stack and a first source/drain region, where the first source/drain region is adjacent to at least one side of the first gate stack, and a second transistor in the PMOS region, including a second gate stack and a second source/drain region, where the second source/drain region is adjacent to at least one side of the second gate stack, where the first gate stack includes a first high dielectric constant insulating film, an insertion layer, a first metal layer and a first protection layer that are sequentially stacked in a first direction, the second gate stack includes a second high dielectric constant insulating film, a second metal layer and a second protection layer that are sequentially stacked in the first direction, an oxygen concentration of the first protection layer is higher than an oxygen concentration of the first metal layer, an oxygen concentration of the second protection layer is higher than an oxygen concentration of the second metal layer, and a lanthanum (La) concentration in the first high dielectric constant insulating film is higher than a lanthanum (La) concentration in the second high dielectric constant insulating film. It shou