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EP-4739032-A1 - STACKED INTEGRATED CIRCUIT DEVICES

EP4739032A1EP 4739032 A1EP4739032 A1EP 4739032A1EP-4739032-A1

Abstract

A stacked integrated circuit device (1000) includes a plurality of nanosheet stack structures, a gate separator, a lower gate electrode, an upper gate electrode, a lower gate cut structure, an upper gate cut structure, and a coupling gate cut structure. The upper gate electrode extends along a side surface of the coupling gate cut structure and is electrically connected to the lower gate electrode.

Inventors

  • MOON, BYUNGHO
  • HWANG, DONGHOON
  • KIM, MINWOO

Assignees

  • SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date
20260506
Application Date
20251022

Claims (15)

  1. A stacked integrated circuit device (100) comprising: a plurality of nanosheet stack structures (NSS) spaced apart from each other in a first direction (X) and a second direction (Y) perpendicular to the first direction (X), the plurality of nanosheet stack structures (NSS) each comprising a lower nanosheet stack structure (LNSS) and an upper nanosheet stack structure (UNSS) on the lower nanosheet stack structure (LNSS); a gate separator (MDI) between the lower nanosheet stack structure (LNSS) and the upper nanosheet stack structure (UNSS) of each of the plurality of nanosheet stack structures (NSS); a lower gate electrode (LGL) extending around the lower nanosheet stack structure (LNSS) of each of the plurality of nanosheet stack structures (NSS); a first upper gate electrode (UGL) extending around the upper nanosheet stack structure (UNSS) of each of the plurality of nanosheet stack structures (NSS); a lower gate cut structure (LCT) and an upper gate cut structure (UCT) on the lower gate cut structure (LCT), the lower gate cut structure (LCT) being between a first pair of lower nanosheet stack structures (LNSS) of a first pair of nanosheet stack structures (NSS) adjacent to each other in the second direction (Y) among the plurality of nanosheet stack structures (NSS), and the upper gate cut structure (UCT) being between a first pair of upper nanosheet stack structures (UNSS) of the first pair of nanosheet stack structures (NSS); and a coupling gate cut structure (MCT) between a second pair of nanosheet stack structures (NSS) adjacent to each other in the second direction (Y) among the plurality of nanosheet stack structures (NSS), wherein the first upper gate electrode (UGL) extends along a side surface of the coupling gate cut structure (MCT) and is electrically connected to the lower gate electrode (LGL).
  2. The stacked integrated circuit device (100) of claim 1, wherein: a portion of the lower gate electrode (LGL) on at least one side of the lower gate cut structure (LCT) is separated from and is not electrically connected to the first upper gate electrode (UGL).
  3. The stacked integrated circuit device (100) of claim 1 or 2, wherein a width of a top surface of the lower gate cut structure (LCT) in the second direction (Y) is greater than a width of a bottom surface of the upper gate cut structure (UCT) in the second direction (Y).
  4. The stacked integrated circuit device (100) of claim 3, wherein the first upper gate electrode (UGL) comprises a first protrusion (UGL-P) extending from a portion of the first upper gate electrode (UGL) that overlaps the gate separator (MDI) and the lower gate cut structure (LCT), optionally a first portion of a top surface of the lower gate cut structure (LCT), in a third direction (Z) that is perpendicular to the first direction (X) and the second direction (Y).
  5. The stacked integrated circuit device (100) of claim 4, wherein a first portion of the top surface of the lower gate cut structure (LCT) overlaps the bottom surface of the upper gate cut structure (UCT) in the third direction (Z), and a second portion of the top surface of the lower gate cut structure (LCT) overlaps a bottom surface of the first protrusion (UGL-P) in the third direction (Z).
  6. The stacked integrated circuit device of claim 4, wherein: a first side surface of the lower gate cut structure (LCT) at least partially overlaps a bottom surface of the first protrusion (UGL-P) of the first upper gate electrode (UG) in the second direction (Y), and a second side surface of the lower gate cut structure (LCT) that is opposite to the first side surface of the lower gate cut structure (LCT) at least partially overlaps a bottom surface of the upper gate cut structure (UCT) in the second direction (Y).
  7. The stacked integrated circuit device (100) of claim 4 or 5, wherein the first protrusion of the first upper gate electrode and a second protrusion of a second upper gate electrode are on opposite sides of the upper gate cut structure in the second direction.
  8. The stacked integrated circuit device (100) of claim 4 or 5, wherein a length of the first protrusion (UGL-P) in the second direction (Y) and a length of a second protrusion (UGL-Pa, UGL-Pb) of a second upper gate electrode (UGL) in the second direction (Y) are equal to each other, and wherein the first protrusion (UGL-P) and the second protrusion (UGL-Pa, UGL-Pb) are on opposite sides of the upper gate cut structure (UCT).
  9. The stacked integrated circuit device (100) of claim 4 or 5, wherein a length of the first protrusion (UGL-P) in the second direction (Y) and a length of a second protrusion (UGL-Pa, UGL-Pb) of a second upper gate electrode (UGL) in the second direction (Y) are different from each other, and wherein the first protrusion (UGL-P) and the second protrusion (UGL-Pa, UGL-Pb) are on opposite sides of the upper gate cut structure (UCT).
  10. The stacked integrated circuit device (100) of any one of claims 4 to 9, wherein the first protrusion (UGL-P) of the first upper gate electrode (UGL) is on a first side of the upper gate cut structure (UCT) in the second direction (Y) and is not on a second side of the upper gate cut structure (UCT) that is opposite to the first side of the upper gate cut structure (UCT).
  11. The stacked integrated circuit device (100) of any one of claims 1 to 10, wherein a number of lower nanosheets (LNS) of the lower nanosheet stack structure (LNSS) is greater than a number of upper nanosheets (UNS) of the upper nanosheet stack structure (UNSS).
  12. The stacked integrated circuit device (100) of any one of claims 1 to 11, wherein: the lower nanosheet stack structure (LNSS) comprises a plurality of lower nanosheets (LNS) spaced apart from each other in a third direction (Z) that is perpendicular to the first direction (X) and the second direction (Y), the upper nanosheet stack structure (UNSS) includes a plurality of upper nanosheets (UNS) spaced apart from each other in the third direction (Z), and a width of each of the plurality of lower nanosheets (LNS) in the second direction (Y) is greater than a width of each of the plurality of upper nanosheets (UNS) in the second direction (Y).
  13. The stacked integrated circuit device (100) of any one of claims 1 to 12, further comprising wherein the first upper gate electrode (UGL) comprises a connection extension (GL-E) extending along a side surface of the coupling gate cut structure (MCT) and is electrically connected to the lower gate electrode (LGL).
  14. The stacked integrated circuit device (100) of claim 13, wherein the connection extension (GL-E) of the first upper gate electrode (UGL) extends between the coupling gate cut structure (MCT) and the gate separator (MDI) and between the coupling gate cut structure (MCT) and the lower gate electrode (LGL).
  15. The stacked integrated circuit device of claim 1, wherein a portion of the lower gate electrode (LGL) on at least one side of the lower gate cut structure (LCT) is separated, by the gate separator (MDI) and the lower gate cut structure (LCT), from the upper gate electrode (UGL).

Description

TECHNICAL FIELD The present disclosure relates to integrated circuit devices, and more particularly, to a stacked integrated circuit devices. BACKGROUND With the development of electronics technology, down-scaling of integrated circuit devices has been in rapid progress. In addition, to increase the integration density of integrated circuit devices, there has been research into stacked integrated circuit devices. SUMMARY The present disclosure provides stacked integrated circuit devices capable of scaling down. According to an aspect of the present disclosure, there is provided a stacked integrated circuit device including a plurality of nanosheet stack structures spaced apart from each other in a first direction and a second direction perpendicular to the first direction, the plurality of nanosheet stack structures each including a lower nanosheet stack structure and an upper nanosheet stack structure on the lower nanosheet stack structure; a gate separator between the lower nanosheet stack structure and the upper nanosheet stack structure of each of the plurality of nanosheet stack structures; a lower gate electrode extending around the lower nanosheet stack structure of each of the plurality of nanosheet stack structures; a first upper gate electrode extending around the upper nanosheet stack structure of each of the plurality of nanosheet stack structures; a lower gate cut structure and an upper gate cut structure on the lower gate cut structure, the lower gate cut structure being between a first pair of lower nanosheet stack structures of a first pair of nanosheet stack structures adjacent to each other in the second direction among the plurality of nanosheet stack structures, and the upper gate cut structure being between a first pair of upper nanosheet stack structures of the first pair of nanosheet stack structures; and a coupling gate cut structure between a second pair of nanosheet stack structures adjacent to each other in the second direction among the plurality of nanosheet stack structures, where the first upper gate electrode extends along a side surface of the coupling gate cut structure and is electrically connected to the lower gate electrode. According to another aspect of the present disclosure, there is provided a stacked integrated circuit device including a plurality of nanosheet stack structures spaced apart from each other in a first direction and a second direction perpendicular to the first direction, the plurality of nanosheet stack structures each including a lower nanosheet stack structure and an upper nanosheet stack structure on the lower nanosheet stack structure; an intermediate insulating layer between the lower nanosheet stack structure and the upper nanosheet stack structure of each of the plurality of nanosheet stack structures; a lower gate electrode extending around the lower nanosheet stack structure of each of the plurality of nanosheet stack structures; a first upper gate electrode extending surrounding the upper nanosheet stack structure of each of the plurality of nanosheet stack structures; a lower gate cut structure and an upper gate cut structure on the lower gate cut structure, the lower gate cut structure being between a first pair of lower nanosheet stack structures of a first pair of nanosheet stack structures adjacent to each other in the second direction among the plurality of nanosheet stack structures, and the upper gate cut structure being between a first pair of upper nanosheet stack structures of the first pair of two nanosheet stack structures; and a coupling gate cut structure a second pair of nanosheet stack structures adjacent to each other in the second direction among the plurality of nanosheet stack structures, where the first upper gate electrode includes a connection extension and a first protrusion, where the connection extension extends along a side surface of the coupling gate cut structure and is electrically connected to the lower gate electrode, and where the first protrusion extends from a portion of the first upper gate electrode that overlaps the intermediate insulating layer and the lower gate cut structure in a third direction that is perpendicular to the first direction and the second direction. According to a further aspect of the present disclosure, there is provided a stacked integrated circuit device including a plurality of nanosheet stack structures spaced apart from each other in a first direction and a second direction perpendicular to the first direction, the plurality of nanosheet stack structures each including a lower nanosheet stack structure and an upper nanosheet stack structure on the lower nanosheet stack structure, the lower nanosheet stack structure including a plurality of lower nanosheets spaced apart from each other in a third direction that is perpendicular to the first direction and the second direction, and the upper nanosheet stack structure including a plurality of upper nanosheets spaced apart from ea