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EP-4739034-A1 - SEMICONDUCTOR DEVICE

EP4739034A1EP 4739034 A1EP4739034 A1EP 4739034A1EP-4739034-A1

Abstract

A semiconductor device includes a substrate including a logic cell region and an ESD cell region, a plurality of active fins on the ESD cell region, disposed alternately in a first direction, including first active fins and second active fins disposed alternately and spaced apart in the first direction, a device isolation layer defining the first and second active fins, a pair of source/drain patterns on each of the plurality of active fins, spaced apart from each other in a second direction intersecting the first direction, a channel pattern between the pair of source/drain patterns, and a gate electrode extending in the first direction on the channel pattern, wherein each of the first and second active fins extending in the second direction, and a length of the first active fin in the second direction is greater than a length of the second active fin in the second direction.

Inventors

  • YOO, JAE-HYUN
  • PARK, YONGHEE
  • PARK, SO RA
  • SHIN, DONG-GWAN

Assignees

  • Samsung Electronics Co., Ltd.

Dates

Publication Date
20260506
Application Date
20250602

Claims (15)

  1. A semiconductor device comprising: a substrate (100) including a logic cell region and an electrostatic discharge, ESD, cell region; a plurality of active fins (AF1, AF2) on the ESD cell region alternating in a first direction (D1), the plurality of active fins (AF1, AF2) including first active fins (AF1) and second active fins (AF2) alternating and spaced apart in the first direction (D1); a device isolation layer (ST) defining the first active fins (AF1) and the second active fins (AF2); a pair of source/drain patterns (121, 122) on each of the plurality of active fins (AF1, AF2) and spaced apart from each other in a second direction (D2) intersecting the first direction (D1); a channel pattern (CH) between the pair of source/drain patterns (121, 122); and a gate electrode (GE) extending in the first direction (D1) on the channel pattern (CH), wherein each of the first (AF1) and second (AF2) active fins extend in the second direction (D2), and a length of the first active fin (AF1) in the second direction (D2) is greater than a length of the second active fin (AF2) in the second direction (D2).
  2. The semiconductor device of claim 1, wherein the length of the first active fin (AF1) in the second direction (D2) is 1.5 to 3.5 times the length of the second active fin (AF2) in the second direction (D2).
  3. The semiconductor device of claim 1 or 2, further comprising: a first portion of a N+ emitter region (121), a first portion of a P+ base region (140), an N collector region (122), a second portion of the P+ base region (140), and a second portion of the N+ emitter region (121) sequentially arranged in the second direction (D2) on each of the first active fins (AF1).
  4. The semiconductor device of any preceding claim, further comprising: a first N+ emitter region (121), a first portion of a P+ base region (140), an N collector region (122), a second portion of the P+ base region (140), and a second N+ emitter region (121_C) sequentially arranged in the second direction (D2) on each of the second active fins (AF2).
  5. The semiconductor device of any preceding claim, further comprising: a third active fin (AF2) spaced apart from each of the second active fins (AF2) by a certain distance in the second direction (D2).
  6. The semiconductor device of claim 5, further comprising: a first N+ emitter region (121), a first portion of a first P+ base region (140), a first N collector region (122), a second portion of the first P+ base region (140), and a second N+ emitter region (121_C) sequentially arranged in the second direction (D2) on each of the second active fins (AF2); and a third N+ emitter region (121_C), a second portion of a second P+ base region (140), a second N collector region (122), a first portion of the second P+ base region (140), and a fourth N+ emitter region (121) sequentially disposed in the second direction (D2) on each of the third active fins (AF2).
  7. The semiconductor device of claim 6, wherein a width of the second N+ emitter region (121_C) on each of the second active fins (AF2) in the second direction (D2) is less than a width of the first N+ emitter region (121) on each of the second active fins (AF2) in the second direction (D2), and a width of the third N+ emitter region (121_C) on the third active fin (AF2) in the second direction (D2) is less than a width of the fourth N+ emitter region (121) on each of the third active fins (AF2) in the second direction (D2).
  8. The semiconductor device of any preceding claim, further comprising: an NPN bipolar transistor on each of the first active fins (AF1).
  9. The semiconductor device of any preceding claim, wherein a distance between one of the first active fins (AF1) and one of the second active fins (AF2) is a first width (W1), and a distance between adjacent first active fins (AF1) among the first active fins (AF1) is a second width (W2), different from the first width (W1).
  10. The semiconductor device of claim 9, wherein the second width (W2) is greater than the first width (W1).
  11. The semiconductor device of any preceding claim, further comprising: an active contact (AC) electrically connected to each of the pair of source/drain patterns (121, 122); and a gate contact (GC) electrically connected to the gate electrode (GE).
  12. The semiconductor device of any preceding claim, wherein an active contact connected (AC) to the pair of source/drain patterns (121, 122) and a gate contact (GC) connected to the gate electrode (GE) are not provided in at least a portion of the ESD cell region.
  13. A semiconductor device comprising: a substrate (100) including an electrostatic discharge, ESD, cell region; a plurality of active fins (AF1, AF2) on the ESD cell region and spaced apart from each other in a first direction (D1); a device isolation layer (ST) defining each of the plurality of active fins (AF1, AF2); a pair of source/drain patterns (121, 122) on each of the plurality of active fins (AF1, AF2) and spaced apart from each other in a second direction (D2) intersecting the first direction (D1); a channel pattern (CH) between the pair of source/drain patterns (121, 122); and a gate electrode (GE) extending in the first direction (D1) on the channel pattern (CH), wherein the plurality of active fins (AF1, AF2) include first active fins (AF1) and second active fins (AF2), and at least one of the second active fins (AF2) is between the first active fins (AF1).
  14. The semiconductor device of claim 13, wherein a distance between one of the first active fins (AF1) and one of the second active fins (AF2) is a first width (W1), in response to one of the second active fins (AF2) being between the first active fins (AF1), a distance between the neighboring first active fins (AF1) among the first active fins (AF1) is a second width (W2) different from the first width (W1), and in response to two of the second active fins (AF2) being between the first active fins (AF1), a distance between the neighboring first active fins (AF1) among the first active fins (AF1) is a third width (W3) different from the first width (W1).
  15. The semiconductor device of claim 14, wherein the third width (W3) is greater than the first width (W1) and the second width (W2).

Description

BACKGROUND Some example embodiments relate to a semiconductor device, and more specifically, to a semiconductor device including an ESD device (Electro-Static Discharge device or Electro-Static Discharge cell) having a fin pattern, and/or a method of fabricating the same. Semiconductor devices are widely used in the electronics industry because of their small sizes, multi-functional characteristics, and/or low manufacturing costs. Semiconductor devices may be categorized as one of semiconductor memory devices for storing logical data, semiconductor logic devices for processing logical data, and hybrid semiconductor devices having both the functions of the semiconductor memory devices and the functions of the semiconductor logic devices. As high-speed and/or low-power electronic devices have been in demand, high-speed and/or low-voltage semiconductor devices used therein have also been in demand, and highly integrated semiconductor devices have been pursued to satisfy these demands. However, as the integration densities of semiconductor devices increase, electrical characteristics and/or production yields of the semiconductor devices may be reduced. Thus, techniques for improving electrical characteristics and/or production yields of semiconductor devices have been variously studied. Due to build-up of electrostatic charges in semiconductor devices, relatively high voltages may be generated near integrated circuits. The high voltages may be generated by input or output buffers of the integrated circuit, and/or by a person touching a package pin electrically connected to the input or output buffer (e.g., through the triboelectric effect). When electrostatic charges are discharged, relatively high currents may be generated at the input and output nodes of the integrated circuit. Such electrostatic discharge (ESD) may destroy or damage the entire integrated circuit. Accordingly, the research has been conducted to electrically ground the current caused by electrostatic discharge of semiconductor devices so as to reduce or mitigate such damage. At least some of the above and other features of the invention are set out in the claims. SUMMARY According to some example embodiments, a semiconductor device with improved reliability and/or yield may be provided. Problems solved or improve upon by example embodiments are not limited to the problems mentioned above, and other problems not mentioned may be clearly understood by those of ordinary skill in the art from the description below. A semiconductor device according to some example embodiments may include a substrate including a logic cell region and an ESD cell region, a plurality of active fins on the ESD cell region, the plurality of active fins alternating in a first direction, including first active fins and second active fins alternating and spaced apart in the first direction, a device isolation layer defining the first active fins and the second active fins, a pair of source/drain patterns on each of the plurality of active fins, spaced apart from each other in a second direction intersecting the first direction, a channel pattern between the pair of source/drain patterns, and a gate electrode extending in the first direction on the channel pattern. Each of the first and second active fins extending in the second direction, and a length of the first active fin in the second direction is greater than a length of the second active fin in the second direction. Alternatively or additionally a semiconductor device according to some example embodiments may include a substrate including an ESD cell region, a plurality of active fins on the ESD cell region and spaced apart from each other in a first direction, a device isolation layer defining each of the plurality of active fins, a pair of source/drain patterns on each of the plurality of active fins and spaced apart from each other in a second direction intersecting the first direction, a channel pattern between the pair of source/drain patterns, and a gate electrode extending in the first direction on the channel pattern. The plurality of active fins include first active fins and second active fins, and at least one of the second active fins is between the first active fins. Alternatively or additionally, a semiconductor device according to some example embodiments may include a substrate including a logic cell region and an ESD cell region, a first active pattern and a second active pattern on the ESD cell region, alternating in a first direction, and extending in a second direction intersecting the first direction, a device isolation layer on the ESD cell region and defining the first active pattern and the second active pattern, a channel pattern on the first active pattern, including a first semiconductor pattern and a second semiconductor pattern stacked and spaced apart from each other, a pair of source/drain patterns connected to the channel pattern and spaced apart from each other in the second direction,