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EP-4739036-A1 - CHIP WITH ELECTROSTATIC DISCHARGE PROTECTION

EP4739036A1EP 4739036 A1EP4739036 A1EP 4739036A1EP-4739036-A1

Abstract

A chip with electrostatic discharge protection is shown. The chip has an output driver and an electrostatic discharge (ESD) protection control circuit. The output driver has a first output driver transistor coupled between an input/output (I/O) pad of the chip and ground, and a second output driver transistor coupled between a power source and the I/O pad. The ESD protection control circuit has a first output terminal coupled to a control terminal of the first output driver transistor, to control the first output driver transistor for electrostatic discharge protection. The ESD control circuit is enabled in response to electrostatic disturbance at the I/O pad.

Inventors

  • WU, HAN-HSIN
  • CHEN, YI-LUN

Assignees

  • MEDIATEK INC.

Dates

Publication Date
20260506
Application Date
20250923

Claims (15)

  1. A chip (200) with electrostatic discharge protection, comprising an output driver having a first output driver transistor (M1) coupled between an input/output pad (202) of the chip (200) and ground, and a second output driver transistor (M2) coupled between a power source (VDD) and the input/output pad (202), wherein the chip (200) is characterized in further comprising: an electrostatic discharge protection control circuit (206, 300, 400, 500, 600, 700, 800), having a first output terminal (ESD_CS1) coupled to a control terminal of the first output driver transistor (M1), to control the first output driver transistor (M1) for electrostatic discharge protection, wherein the electrostatic discharge protection control circuit (206, 300, 400, 500, 600, 700, 800) is enabled in response to electrostatic disturbance at the input/output pad (202).
  2. The chip (200) with electrostatic discharge protection as claimed in claim 1, further comprising: an electrostatic discharge clamp (204), coupled between the power source (VDD) and the ground; wherein, the electrostatic discharge protection control circuit (206, 300) turns off the first output driver transistor (M1) in response to positive electrostatic disturbance at the input/output pad (202), and thereby an electrostatic discharge current from the input/output pad (202) is directed to the ground through a parasitic diode of the second output driver transistor (M2) and the electrostatic discharge clamp (204).
  3. The chip (200) with electrostatic discharge protection as claimed in claim 2, wherein: the first output driver transistor (M1) is an n-type metal-oxide-semiconductor field-effect transistor, having a drain terminal coupled to the input/output pad (202), and a source terminal coupled to the ground; and the electrostatic discharge protection control circuit (206, 300) comprises: a resistor (R) and a capacitor (C), coupled between the power source (VDD) and the ground; an inverter (Inv), having an input terminal coupled to a connection terminal between the resistor (R) and the capacitor (C); and a lock transistor (TL), which is an n-type metal-oxide-semiconductor field-effect transistor having a gate terminal coupled to an output terminal of the inverter (Inv), a drain terminal coupled to a gate terminal of the first output driver transistor (M1), and a source terminal coupled to the ground.
  4. The chip (200) with electrostatic discharge protection as claimed in claim 1, wherein: the electrostatic discharge protection control circuit (206, 600) turns on the first output driver transistor (M1) in response to positive electrostatic disturbance at the input/output pad (202), and thereby an electrostatic discharge current from the input/output pad (202) is directed to the ground through the first output driver transistor (M1).
  5. The chip (200) with electrostatic discharge protection as claimed in claim 4, wherein: the first output driver transistor (M1) is an n-type metal-oxide-semiconductor field-effect transistor, having a drain terminal coupled to the input/output pad (202), and a source terminal coupled to the ground; and the electrostatic discharge protection control circuit (206, 600) comprises: a resistor (R) and a capacitor (C), coupled between the power source (VDD) and the ground; and a trigger transistor (TT), which is a p-type metal-oxide-semiconductor field-effect transistor having a gate terminal coupled to a connection terminal between the resistor (R) and the capacitor (C), a source terminal coupled to the power source (VDD), and a drain terminal coupled to a gate terminal of the first output driver transistor (M1).
  6. The chip (200) with electrostatic discharge protection as claimed in claim 1, wherein: the electrostatic discharge protection control circuit (206, 300, 400, 500, 600, 700, 800) further has a second output terminal (ESD_CS2) coupled to a control terminal of the second output driver transistor (M2), to control the second output driver transistor (M2) for electrostatic discharge protection.
  7. The chip (200) with electrostatic discharge protection as claimed in claim 6, further comprising: an electrostatic discharge clamp (204), coupled between the power source (VDD) and the ground; wherein, the electrostatic discharge protection control circuit (206, 400, 500) turns off the second output driver transistor (M2) in response to negative electrostatic disturbance at the input/output pad (202), and thereby an electrostatic discharge current from the power source (VDD) is directed to the input/output pad (202) through the electrostatic discharge clamp (204) and a parasitic diode of the first output driver transistor (M1).
  8. The chip (200) with electrostatic discharge protection as claimed in claim 7, wherein: the second output driver transistor (M2) is a p-type metal-oxide-semiconductor field-effect transistor, having a source terminal coupled to the power source (VDD), and a drain terminal coupled to the input/output pad (202); and the electrostatic discharge protection control circuit (206, 400) comprises: a resistor (R) and a capacitor (C), coupled between the power source (VDD) and the ground; a lock transistor (TL), which is a p-type metal-oxide-semiconductor field-effect transistor having a gate terminal coupled to a connection terminal between the resistor (R) and the capacitor (C), a source terminal coupled to the power source (VDD), and a drain terminal coupled to a gate terminal of the second output driver transistor (M2).
  9. The chip (200) with electrostatic discharge protection as claimed in claim 7, wherein: the second output driver transistor (M2) is an n-type metal-oxide-semiconductor field-effect transistor, having a drain terminal coupled to the power source (VDD), and a source terminal coupled to the input/output pad (202); and the electrostatic discharge protection control circuit (206, 500) comprises: a resistor (R) and a capacitor (C), coupled between the power source (VDD) and the input/output pad (202); an inverter (Inv), having an input terminal coupled to a connection terminal between the resistor (R) and the capacitor (C); and a lock transistor (TL), which is an n-type metal-oxide-semiconductor field-effect transistor having a gate terminal coupled to an output terminal of the inverter (Inv), a drain terminal coupled to a gate terminal of the second output driver transistor (M2), and a source terminal coupled to the input/output pad (202).
  10. The chip (200) with electrostatic discharge protection as claimed in claim 6, wherein: the electrostatic discharge protection control circuit (206, 700, 800) turns on the second output driver transistor (M2) in response to negative electrostatic disturbance at the input/output pad (202), and thereby an electrostatic discharge current from the power source (VDD) is directed to the input/output pad (202) through the second output driver transistor (M2).
  11. The chip (200) with electrostatic discharge protection as claimed in claim 10, wherein: the second output driver transistor (M2) is a p-type metal-oxide-semiconductor field-effect transistor, having a source terminal coupled to the power source (VDD), and a drain terminal coupled to the input/output pad (202); and the electrostatic discharge protection control circuit (206, 700) comprises: a resistor (R) and a capacitor (C), coupled between the power source (VDD) and the ground; an inverter (Inv), having an input terminal coupled to a connection terminal between the resistor (R) and the capacitor (C); and a trigger transistor (TT), which is an n-type metal-oxide-semiconductor field-effect transistor having a gate terminal coupled to an output terminal of the inverter (Inv), a drain terminal coupled to a gate terminal of the second output driver transistor (M2), and a source terminal coupled to the ground.
  12. The chip (200) with electrostatic discharge protection as claimed in claim 10, wherein: the second output driver transistor (M2) is an n-type metal-oxide-semiconductor field-effect transistor, having a drain terminal coupled to the power source (VDD), and a source terminal coupled to the input/output pad (202); and the electrostatic discharge protection control circuit (206, 800) comprises: a resistor (R) and a capacitor (C), coupled between the power source (VDD) and the input/output pad (202); and a trigger transistor (TT), which is a p-type metal-oxide-semiconductor field-effect transistor having a gate terminal coupled to a connection terminal between the resistor (R) and the capacitor (C), a source terminal coupled to the power source (VDD), and a drain terminal coupled to a gate terminal of the second output driver transistor (M2).
  13. A chip (200) with electrostatic discharge protection, comprising an output driver having a first output driver transistor (M1) coupled between an input/output pad (202) of the chip and ground, and a second output driver transistor (M2) coupled between a power source (VDD) and the input/output pad (202), wherein the chip is characterized in further comprising: an electrostatic discharge protection control circuit (206, 300, 400, 500, 600, 700, 800), having an output terminal (ESD_CS2) coupled to a control terminal of the second output driver transistor (M2), to control the second output driver transistor (M2) for electrostatic discharge protection, wherein the electrostatic discharge protection control circuit (206, 300, 400, 500, 600, 700, 800) is enabled in response to electrostatic disturbance at the input/output pad (202).
  14. The chip (200) with electrostatic discharge protection as claimed in claim 13, further comprising: an electrostatic discharge clamp (204), coupled between the power source (VDD) and the ground; wherein, the electrostatic discharge protection control circuit (206, 400, 500) turns off the second output driver transistor (M2) in response to negative electrostatic disturbance at the input/output pad (202), and thereby an electrostatic discharge current from the power source (VDD) is directed to the input/output pad (202) through the electrostatic discharge clamp (204) and a parasitic diode of the first output driver transistor (M1).
  15. The chip (200) with electrostatic discharge protection as claimed in claim 13, wherein: the electrostatic discharge protection control circuit (206, 700, 800) turns on the second output driver transistor (M2) in response to negative electrostatic disturbance at the input/output pad (202), and thereby an electrostatic discharge current from the power source (VDD) is directed to the input/output pad (202) through the second output driver transistor (M2).

Description

TECHNICAL FIELD The present disclosure relates to electrostatic discharge (ESD) protection. BACKGROUND A conventional chip design may use large array devices for electrostatic discharge (ESD) self-protection. If the output driver is incapable of ESD self-protection, additional ESD cells are required. FIG. 1 depicts a conventional ESD protection design for an input/output (I/O) pad 102 of a chip 100. The chip 100 comprises an output driver (a buck converter, for example) formed by a first output driver transistor M1 (coupled between the I/O pad 102 and the ground VSS) and a second output driver M2 (coupled between the power source VDD and the I/O pad 102). In addition to an ESD clamp 104 between the power source VDD and the ground VSS, an ESD pull-up circuit 106 is required between the power source VDD and the I/O pad 102, and an ESD pull-down circuit 108 is required between the I/O pad 102 and the ground VSS. However, the ESD pull-up circuit 106 and the ESD pull-down circuit 108 may result in performance degradation of the chip 100, and may form leakage paths in the normal operations of the chip 100. BRIEF SUMMARY A chip with electrostatic discharge (ESD) protection is shown. Instead of using additional ESD pull-up circuit or ESD pull-down circuit, an electrostatic discharge (ESD) protection control circuit controlling the output driver transistors is shown. A chip with ESD protection in accordance with an exemplary embodiment of the disclosure includes an output driver and an ESD protection control circuit. The output driver has a first output driver transistor coupled between the input/output (I/O) pad of the chip and ground, and a second output driver transistor coupled between a power source and the I/O pad. The ESD protection control circuit has a first output terminal coupled to a control terminal of the first output driver transistor, to control the first output driver transistor for ESD protection. The ESD protection control circuit is enabled in response to electrostatic disturbance at the I/O pad. In an exemplary embodiment, the chip has an electrostatic discharge clamp. The ESD protection control circuit turns off the first output driver transistor in response to positive electrostatic disturbance at the I/O pad, and thereby an electrostatic discharge current from the I/O pad is directed to the ground through a parasitic diode of the second output driver transistor and the electrostatic discharge clamp. In an exemplary embodiment, the ESD protection control circuit turns on the first output driver transistor in response to positive electrostatic disturbance at the I/O pad, and thereby an electrostatic discharge current from the I/O pad is directed to the ground through the first output driver transistor. In an exemplary embodiment, the ESD protection control circuit further has a second output terminal coupled to a control terminal of the second output driver transistor, to control the second output driver transistor for ESD protection. In an exemplary embodiment, the chip has an electrostatic discharge clamp. The ESD protection control circuit turns off the second output driver transistor in response to negative electrostatic disturbance at the I/O pad, and thereby an electrostatic discharge current from the power source is directed to the I/O pad through the electrostatic discharge clamp and a parasitic diode of the first output driver transistor. In an exemplary embodiment, the ESD protection control circuit turns on the second output driver transistor in response to negative electrostatic disturbance at the I/O pad, and thereby an electrostatic discharge current from the power source is directed to the I/O pad through the second output driver transistor. In an exemplary embodiment, the ESD protection control circuit only controls the second output driver transistor in response to negative electrostatic disturbance at the I/O pad. A detailed description is given in the following embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: FIG. 1 depicts a conventional ESD protection design for an input/output (I/O) pad 102 of a chip 100;FIG. 2 shows a chip 200 in accordance with an exemplary embodiment of the disclosure;FIG. 3A and FIG. 3B show the ESD locking for the first output driver transistor M1 in accordance with an exemplary embodiment of the disclosure;FIG. 4A and FIG. 4B show the ESD locking for the second output driver transistor M2 in accordance with an exemplary embodiment of the disclosure;FIG. 5A and FIG. 5B show the ESD locking for an NMOS M2 in accordance with an exemplary embodiment of the disclosure;FIG. 6A and FIG. 6B show the ESD protection based on MOS triggering of the first output driver transistor M1 in accordance with an exemplary embodiment of the disclosure;FIG. 7A an