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EP-4739063-A1 - SEMICONDUCTOR STRUCTURE

EP4739063A1EP 4739063 A1EP4739063 A1EP 4739063A1EP-4739063-A1

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate, electronic devices, and an interconnection structure. The electronic devices are disposed on the substrate. The electronic devices includes first gate structures. The interconnection structure including a first interconnection-level conductive trace is located directly above the electronic devices. The first interconnection-level conductive trace has first openings for exposing at least one of the first gate structures.

Inventors

  • WU, Yu-sheng
  • JI, YAN-LIANG

Assignees

  • MEDIATEK INC.

Dates

Publication Date
20260506
Application Date
20251007

Claims (15)

  1. A semiconductor structure (500A, 500B), comprising: a substrate (200); electronic devices (220) disposed on the substrate, wherein the electronic devices comprise first gate structures (210-1); and an interconnection structure (260) comprising a first interconnection-level conductive trace (Mtop, Mn) located directly above the electronic devices, wherein the first interconnection-level conductive trace has first openings (250, 250A, 250B, 250C) for exposing at least one of the first gate structures.
  2. The semiconductor structure as claimed in claim 1, wherein a first space (S1, S2) between the two adjacent first openings in a first direction (100) satisfies Equation (1): S 1 = mλ D 1 / A 1 wherein S1 is the first space between the two adjacent first openings, D1 is a first distance between the first interconnection-level conductive trace and the electronic devices in a second direction (120), A1 is a first dimension of the first opening in the first direction, λ is the wavelength of the light, and m is greater than 1 and less than 3.
  3. The semiconductor structure as claimed in claim 2, wherein A1 is greater than or equal to λ.
  4. The semiconductor structure as claimed in claim 1, wherein the first interconnection-level conductive trace is a topmost interconnection-level conductive trace (Mtop).
  5. The semiconductor structure as claimed in claim 1, wherein the electronic devices are located within a projection of an outer edge (E1, E2) of the first interconnection-level conductive trace on a top surface of the substrate.
  6. The semiconductor structure as claimed in claim 2, wherein in the first direction, the electronic devices are arranged with a cell pitch (P1), and a ratio of the first space to the cell pitch is between 1 and 2; and/or wherein in the first direction, the electronic devices are arranged with a cell pitch (P1), the first openings are arranged with a first pitch (S1), and a ratio of the first pitch to the cell pitch is between 1 and 2.
  7. The semiconductor structure as claimed in any one of claims 1 to 6, wherein each of the electronic devices comprises: a floating gate transistor (220T1) disposed on a first well region (206) in the substrate, wherein the floating gate transistor comprises: one of the first gate structures; and a first source/drain doped region (208DS) and a second source/drain doped region (208D) disposed on the first well region and on opposite sides of the first gate structure; a select transistor (220T2) disposed on the first well region, wherein the select transistor comprises: a second gate structure (220-2) located beside the first gate structure of the floating gate transistor; and a third source/drain (208S) doped region and the first source/drain doped region disposed on the first well region and on opposite sides of the second gate structure.
  8. The semiconductor structure as claimed in claim 7, wherein at least one of the second gate structures (220-2) of the electronic devices are exposed from the first openings (250, 250A, 250B, 250C).
  9. The semiconductor structure as claimed in claim 1, wherein the first openings (250, 250A, 250B, 250C) extend along an extending direction of the corresponding first gate structures (210-1).
  10. The semiconductor structure as claimed in claim 1, wherein the first openings (250, 250A, 250B, 250C) are arranged in rows along an extending direction of the corresponding first gate structures (210-1).
  11. The semiconductor structure as claimed in claim 10, wherein the first openings (250, 250A, 250B, 250C) in the adjacent rows are alternately arranged along the extending direction of the corresponding first gate structures (210-1).
  12. The semiconductor structure as claimed in claim 10, wherein in a top view, the first openings (250, 250A, 250B, 250C) and the first gate structures (210-1) exposed from the corresponding first openings are in a one-to-many relationship or a one-to-one relationship.
  13. The semiconductor structure as claimed in claim 1, wherein the first openings (250, 250A, 250B, 250C) are strip-shaped, square-shaped, circular-shaped, oval-shaped, or polygonal-shaped.
  14. The semiconductor structure as claimed in claim 2, wherein the interconnection structure further comprises: a second interconnection-level conductive trace (Mtop, Mn) overlapping the first interconnection-level conductive trace, wherein the second interconnection-level conductive trace is located directly above or below the first interconnection-level conductive trace, and wherein the second interconnection-level conductive trace has second openings aligned with the corresponding first openings in the second direction.
  15. The semiconductor structure as claimed in claim 14, wherein a second space (S1, S2) between the two adjacent second openings in the first direction satisfies Equation (2): S 2 = pλ D 2 / A 2 wherein S2 is the second space between the two adjacent second openings in the first direction, D2 is a second distance between the second interconnection-level conductive trace and the electronic devices in the second direction, A2 is a third dimension of the second opening in the first direction, λ is the wavelength of light, and p is greater than 1 and less than 3.

Description

BACKGROUND OF THE DISCLOSURE Field of the Disclosure The present disclosure relates to a semiconductor structure, and, in particular, to the layout of an interconnection-level conductive trace of a semiconductor structure. Description of the Related Art During the process of fabricating semiconductor devices such as transistors and memories, unwanted charges may be trapped in a gate oxide layer. These trapped charges may have negative effects on the threshold voltage of the transistor, the program and erase threshold of the memory, the switching speed of the transistor, and the program and erase speed of the memory, for example. Therefore, a novel semiconductor structure is needed. BRIEF SUMMARY OF THE DISCLOSURE An embodiment of the disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, electronic devices, and an interconnection structure. The electronic devices are disposed on the substrate. The electronic devices includes first gate structures. The interconnection structure including a first interconnection-level conductive trace is located directly above the electronic devices. The first interconnection-level conductive trace has first openings for exposing at least one of the first gate structures. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: FIG. 1 is a schematic cross-sectional view of a semiconductor structure in accordance with some embodiments of the disclosure;FIG. 2 is a schematic cross-sectional view of a semiconductor structure in accordance with some embodiments of the disclosure;FIG. 3 is a schematic top view of the semiconductor structure of FIG. 1 or FIG. 2 in accordance with some embodiments of the disclosure, showing the arrangements of openings of an interconnection-level conductive trace of an interconnection structure and the relative positions between the openings of the interconnection-level conductive trace and gate electrodes of electronic devices; andFIGS. 4, 5, 6, 7 and 8 are schematic top views of the interconnection-level conductive trace of the semiconductor structure of FIG. 1 or FIG. 2 in accordance with some embodiments of the disclosure, showing various shapes of the openings of the interconnection-level conductive trace of the interconnection structure. DETAILED DESCRIPTION OF THE DISCLOSURE The following description is made for the purpose of illustrating the general principles of the disclosure and should not be taken in a limiting sense. The scope of the disclosure is best determined by reference to the appended claims. In order to remove the unwanted charges trapped in the gate oxide layers of the semiconductor devices, UV light is usually used to irradiate the transistors and memories after the fabrication of the semiconductor devices. However, the conventional metal routings above the semiconductor devices having gate oxide (GOX) sensitive regions need to be rearranged in other locations to avoid blocking UV light. The rearranged metal routings may cause an increase in the device area and will not facilitate the scaling of the semiconductor devices. FIG. 1 is a schematic cross-sectional view of a semiconductor structure 500A in accordance with some embodiments of the disclosure. FIG. 3 is a schematic top view of the semiconductor structure 500A of FIG. 1 in accordance with some embodiments of the disclosure, showing the arrangements of openings 250 of a first interconnection-level conductive trace Mtop of an interconnection structure 260 and the relative positions between the openings 250 of the first interconnection-level conductive trace Mtop and gate structures 210-1 of electronic devices 220. FIG. 3 only show some features for illustration, and the remaining features may be shown in the cross-sectional views of FIG. 1. In FIG. 1 and the following figures, a direction 100 may be referred to as a channel length direction, a direction 110 may be referred to as a channel width direction, and a direction 120 may be referred to as a device height direction. The directions 100 and 110 are substantially parallel to a top surface 200T of a substrate 200 of the semiconductor structure 500A. The direction 120 is substantially perpendicular to the top surface 200T of the substrate 200 of the semiconductor structure 500A. In some embodiments, the semiconductor structure 500A is applied in logic devices, memory devices or other applicable active devices or passive devices. In some embodiments as shown in FIG. 1, the semiconductor structure 500A is applied in memory devices such as one-time programmable (OTP) memory devices. In some embodiments, the semiconductor structure 500A includes the substrate 200, electronic devices 220 and an interconnection structure 260. As shown in FIG. 1, the substrate 200 has an active region 300 surrounded by isolation features 204. In some embo