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EP-4739064-A2 - PACKAGE ON PACKAGE (POP) DEVICE COMPRISING SOLDER CONNECTIONS BETWEEN INTEGRATED CIRCUIT DEVICE PACKAGES

EP4739064A2EP 4739064 A2EP4739064 A2EP 4739064A2EP-4739064-A2

Abstract

Some features pertain to a package on package (PoP) device that includes a first package, a first solder interconnect coupled to the first integrated circuit package, and a second package coupled to the first package through the first solder interconnect. The second package includes a first die, a package interconnect comprising a first pad, where the first solder interconnect is coupled to the first pad of the package interconnect. The second package also includes a redistribution portion coupled to the first die and the package interconnect, an encapsulation layer at least partially encapsulating the first die and the package interconnect. The first pad may include a surface that has low roughness. The encapsulation layer may encapsulate the package interconnect such that the encapsulation layer encapsulates at least a portion of the first solder interconnect.

Inventors

  • KESER, LIZABETH, ANN
  • RAE, David, Fraser

Assignees

  • QUALCOMM Incorporated

Dates

Publication Date
20260506
Application Date
20160422

Claims (15)

  1. A package on package, PoP, device comprising: a first package; a first solder interconnect coupled to the first package; and a second package coupled to the first package through the first solder interconnect, wherein the second package comprises: a first die; means for interconnecting package portions coupled to the first solder interconnect; a redistribution portion coupled to the first die and the means for interconnecting package portions; and an encapsulation layer at least partially encapsulating the first die and the means for interconnecting package portions, wherein the encapsulation layer at least partially encapsulates the means for interconnecting package portions such that the encapsulation layer encapsulates at least a portion of the first solder interconnect.
  2. The package on package, PoP, device of claim 1, wherein the means for interconnecting package portions comprises a first via.
  3. The package on package, PoP, device of claim 1 or 2, wherein the encapsulation layer touches the first solder interconnect.
  4. The package on package, PoP, device of any of claims 1 to 3, further comprising a solder resist layer on the encapsulation layer.
  5. The package on package, PoP, device of claim 4, wherein the solder resist layer is coupled to the first solder interconnect.
  6. The package on package, PoP, device of any of claims 1 to 5, further comprising a pad located over the first solder interconnect.
  7. The package on package, PoP, device of claim 6, wherein the solder resist layer is coupled to the pad and/or wherein the pad is at least partially located in the solder resist layer.
  8. The package on package, PoP, device of claim 1, wherein the first solder interconnect comprises: a first portion comprising a first property; a second portion comprising a second property; and a third portion comprising a third property.
  9. The package on package, PoP, device of claim 5, wherein the second portion and the third portion of the first solder interconnect comprises an intermetallic material, and/or wherein the second portion is thicker than the third portion.
  10. The package on package, PoP, device of claim 1, wherein the first die is configured to be electrically coupled to the means for interconnecting package portions through the redistribution portion.
  11. The package on package, PoP, device of claim 10, wherein the redistribution portion comprises: at least one dielectric layer; and at least one redistribution layer, wherein the first die is configured to be electrically coupled to the means for interconnecting package portions through the at least one redistribution layer.
  12. The package on package, PoP, device of claim 1, wherein the first package comprises: a package substrate; and a second die.
  13. The package on package, PoP, device of claim 1, wherein the first package comprises a second die and a third die.
  14. The package on package, PoP, device of claim 1, wherein the means for interconnecting package portions is a package interconnect from the group of package interconnects consisting of a printed circuit board, PCB, bar, a preformed through substrate via, TSV, bar, and/or an in-situ plated metal interconnect; and/or wherein the first package is a package from the group of packages consisting of a fan out wafer level package, FOWLP, a wire bond chip scale package, CSP, and/or a flip chip chip scale package, CSP.
  15. The package on package, PoP, device of claim 1, wherein the package on package, PoP, device is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in a automotive vehicle, and further including the device.

Description

BACKGROUND Claim of Priority / Claim of Benefit The present application claims priority to U.S. Provisional Application No. 62/152,663 titled "Package on Package (POP) Device Comprising Improved Solder Connection Between Integrated Circuit Device Packages", filed April 24, 2015, and U.S. Non-Provisional Application No. 14/837,917 titled "Package on Package (POP) Device Comprising Solder Connections between Integrated Circuit Device Packages", filed August 27, 2015, which are hereby expressly incorporated by reference herein. Field Various features relate generally to a package on package (PoP) device, and more specifically to a package on package (PoP) device that includes solder connections between integrated circuit (IC) packages. Background FIG. 1 illustrates a device 100 that includes a first package 102 and an interposer 104. The first package 102 includes a first die 120 and a first package substrate 122. The first package substrate 122 includes a plurality of pads 124 and a first pad 126. The first package substrate 122 also includes a first dielectric layer 123. The first package substrate 122 may also include a first solder resist layer 127. The first solder resist layer 127 is located on the first dielectric layer 123. The first solder resist layer 127 may also cover a portion of the first pad 126. The first die 120 is coupled to the first package substrate 122 through a first plurality of solder balls 128. Specifically, the first die 120 is coupled to the first plurality of pads 124 through the first plurality of solder balls 128. A second plurality of solder balls 130 is coupled to the first package substrate 122. The interposer 104 includes a second pad 146. The interposer 104 may be a package substrate of a second package (not shown). The interposer 104 also includes a second dielectric layer 143. The interposer 104 may also include a second solder resist layer 147. The second solder resist layer 147 is located on the second dielectric layer 143. The second solder resist layer 147 may also cover a portion of the second pad 146. The interposer 104 is coupled to the first package 102 through a first solder ball 156. For example, the first solder ball 156 is coupled to the first pad 126 of the first package substrate 122, and the second pad 146 of the interposer 104. The solder ball 156 is located in a cavity of an encapsulation layer 150 of the first package 102. The cavity of the encapsulation layer 150 in which the solder ball 156 is located in is formed by using a laser process (e.g., laser ablation). As shown in FIG. 1, the first pad 126 has a surface that is in contact with the solder ball 156. The surface of the first pad 126 that is in contact with the solder ball 156 has a relatively rough surface roughness. This is due to the fact that a laser is used to remove the encapsulation layer 150 over the first pad 126. The result of this laser process (e.g., laser ablation) is an uneven surface (e.g., rough surface) on the first pad 126. An uneven surface or rough surface on the first pad 126 can result in a weak joint, a poor joint and/or an open joint between the first pad 126 and the solder ball 156. A weak joint or poor joint connection can result in poor and/or unreliable signal quality in the device 100, which can cause poor performance in the device 100. Therefore, there is a need for a device (e.g., package on package (PoP) device) with strong and reliable joints to ensure better quality and/or performance signals between packages. Ideally, such a device will have a better form factor, be cheaper to fabricate, while at the same time meeting the needs and/or requirements of mobile and/or wearable devices. SUMMARY Various features relate generally to a package on package (PoP) device, and more specifically to a package on package (PoP) device that includes solder connections between integrated circuit (IC) packages. One example provides a package on package (PoP) device that includes a first package, a first solder interconnect coupled to the first package, and a second package coupled to the first package through the first solder interconnect. The second package includes a first die, a package interconnect comprising a first pad, where the first solder interconnect is coupled to the first pad of the package interconnect, and a redistribution portion coupled to the first die and the package interconnect, and an encapsulation layer encapsulating the first die and the package interconnect. Another example provides a package on package (PoP) device that includes a first package, a first solder interconnect coupled to the first package, and a second package coupled to the first package through the first solder interconnect. The second package includes a first die, means for interconnecting package portions coupled to the first solder interconnect, a redistribution portion coupled to the first die and the means for interconnecting package portions, and an encapsulation layer encapsulating the