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EP-4739067-A1 - FIDUCIAL MARK PROTECTION IN AN INTEGRATED CIRCUIT PACKAGE

EP4739067A1EP 4739067 A1EP4739067 A1EP 4739067A1EP-4739067-A1

Abstract

An example carrier substrate of an integrated circuit (IC) includes: a top surface configured to support a semiconductor die; a bottom surface configured to support solder balls; a plurality of fiducial marks disposed on a surface area comprising at least one of the top surface or the bottom surface, the plurality of fiducial marks comprising metal portions; a first solder resist disposed on the plurality of fiducial marks; and a second solder resist disposed on the surface area other than over the first solder resist, the first solder resist having contrast with respect to the second solder resist.

Inventors

  • ZHAO, SAM ZIQUN
  • TSANG, KWOK CHEUNG
  • KIM, HAK NAM
  • SANDHU, JAVED IQBAL
  • HUANG, WEN HSIEN
  • TSAU, LIMING

Assignees

  • Avago Technologies International Sales Pte. Limited

Dates

Publication Date
20260506
Application Date
20251029

Claims (15)

  1. A carrier substrate of an integrated circuit (IC), comprising: a top surface configured to support a semiconductor die; a bottom surface configured to support solder balls; a plurality of fiducial marks disposed on a surface area comprising at least one of the top surface or the bottom surface, the plurality of fiducial marks comprising metal portions; a first solder resist disposed on the plurality of fiducial marks; and a second solder resist disposed on the surface area other than over the first solder resist, the first solder resist having contrast with respect to the second solder resist.
  2. The carrier substrate of claim 1, wherein the first solder resist has a different brightness than the second solder resist.
  3. The carrier substrate of claim 1 or 2, wherein the first solder resist is a different color than the second solder resist.
  4. The carrier substrate of any one of the claims 1 to 3, wherein the first solder resist is a first dielectric material different than a second dielectric material of the second solder resist.
  5. The carrier substrate of any one of the claims 1 to 3, wherein the first and second solder resists are the same dielectric material.
  6. The carrier substrate of any one of the claims 1 to 4, wherein the contrast between the first solder resist and the second solder resist is detectable by an optical alignment system.
  7. The carrier substrate of any one of the claims 1 to 6, further comprising: layers of metallization separated by layers of dielectric, the top surface being a top layer of metallization and the bottom surface being a bottom layer of metallization.
  8. An integrated circuit (IC), comprising: a carrier substrate having a top surface and a bottom surface; a semiconductor die electrically and mechanically mounted to the top surface of the carrier substrate; solder balls electrically and mechanically mounted to the bottom surface of the carrier substrate; a plurality of fiducial marks disposed on a surface area comprising at least one of the top surface or the bottom surface, the plurality of fiducial marks comprising metal portions; a first solder resist disposed on the plurality of fiducial marks; and a second solder resist disposed on the surface area other than over the first solder resist, the first solder resist having contrast with respect to the second solder resist.
  9. The IC of claim 8, wherein the first solder resist has a different brightness than the second solder resist.
  10. The IC of claim 8 or 9, wherein the first solder resist is a different color than the second solder resist.
  11. The IC of any one of the claims 8 to 10, wherein the first solder resist is a first dielectric material different than a second dielectric material of the second solder resist.
  12. The IC of any one of the claims 8 to 10, wherein the first and second solder resists are the same dielectric material.
  13. The IC of any one of the claims 8 to 11, wherein the contrast between the first solder resist and the second solder resist is detectable by an optical alignment system.
  14. The IC of any one of the claims 8 to 13, further comprising: layers of metallization separated by layers of dielectric, the top surface being a top layer of metallization and the bottom surface being a bottom layer of metallization.
  15. A method of fabricating a carrier substrate for an integrated circuit (IC), the method comprising: forming the carrier substrate having a top surface configured to support a semiconductor die and a bottom surface configured to support solder balls; forming a plurality of fiducial marks on a surface area comprising at least one of the tope surface or the bottom surface, the plurality of fiducial marks comprising metal portions; depositing a first solder resist on the plurality of fiducial marks; and depositing a second solder resist disposed on the surface area other than over the first solder resist, the first solder resist having contrast with respect to the second solder resist.

Description

BACKGROUND Fiducial marks can be markers used in integrated circuit (IC) packaging to assist in alignment and positioning during various stages of the manufacturing and assembly process. On a carrier substrate, for example, fiducial marks can be used on the top surface for alignment during flip-chip die attachment, formation of passive components, and the like. Fiducial marks can be used on the bottom surface of the carrier substrate (e.g., the ball grid array (BGA) side) for alignment during solder ball attachment to package substrate as well as during surface mount of the IC device package onto application system board through reflow soldering process. Fiducial marks can be detected by an optical alignment system during the manufacturing and assembly process to perform alignment in the various stages. One technique for forming fiducial marks can be to expose a copper pattern under a solder mask on a surface of the carrier substrate (e.g., top surface, bottom surface, or both). The exposed copper can create a pattern of color contrast that is recognizable by the optical alignment system so that the optical alignment system can identify the fiducial marks and their positions. The exposed copper pattern can be coated with a layer of organic solder preservative (OSP) to prevent oxidation and corrosion. The OSP, however, can break down when heated during some stages, such as solder ball reflow, which may then expose the underlying copper pattern to the environment. Exposed copper fiducial marks can become corroded and discolored in the open air, which can cause the optical alignment system to fail to recognize the fiducial marks during alignment. Further, the exposed copper pattern can react with oxygen and water in a humid and hot environment to generate rust and conductive ions, which can become the source of conductive and free-moving ions in a humid and hot environment in addition to discoloring the color pattern of the exposed copper. The unconstrained conductive ions of the exposed copper can cause electrical shorting of exposed terminals, such as passive components on the carrier substrate top surface and solder balls on the bottom surface. SUMMARY In some embodiments, a carrier substrate of an integrated circuit (IC) can include a top surface configured to support a semiconductor die and a bottom surface configured to support solder balls. The carrier substrate can include a plurality of fiducial marks disposed on a surface area comprising at least one of the top surface or the bottom surface. The plurality of fiducial marks can comprise metal portions. The carrier substrate can include a first solder resist disposed on the plurality of fiducial marks. The carrier substrate can include a second solder resist disposed on the surface area other than over the first solder resist. The first solder resist can have contrast with respect to the second solder resist. In some embodiments, an integrated circuit (IC) can include a carrier substrate having a top surface and a bottom surface, a semiconductor die electrically and mechanically mounted to the top surface of the carrier substrate, and solder balls electrically and mechanically mounted to the bottom surface of the carrier substrate. The IC can include a plurality of fiducial marks disposed on a surface area comprising at least one of the top surface or the bottom surface. The plurality of fiducial marks can comprise metal portions. The IC can include a first solder resist disposed on the plurality of fiducial marks. The IC can include a second solder resist disposed on the surface area other than over the first solder resist. The first solder resist can have contrast with respect to the second solder resist. In some embodiments, a method of fabricating a carrier substrate for an integrated circuit (IC) is described. The method can include forming the carrier substrate having a top surface configured to support a semiconductor die and a bottom surface configured to support solder balls. The method can include forming a plurality of fiducial marks on a surface area comprising at least one of the tope surface or the bottom surface. The plurality of fiducial marks can comprise metal portions. The method can include depositing a first solder resist on the plurality of fiducial marks. The method can include depositing a second solder resist disposed on the surface area other than over the first solder resist. The first solder resist can have contrast with respect to the second solder resist. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a side-view of an integrated circuit (IC) according to some embodiments.Fig. 2A is a top-view of a carrier substrate surface according to some embodiments.Fig. 2B is a cross-section view of surface taken along the line A-A of Fig. 2A according to some embodiments.Fig. 3 is a flow diagram depicting a method of fabricating a carrier substrate with fiducial marks according to embodiments.Fig. 4A is a top-view of a carrier substrate