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EP-4739068-A1 - SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE ASSEMBLY WITH EDGE INTERCONNECTION AND METHOD OF FORMING THE SAME

EP4739068A1EP 4739068 A1EP4739068 A1EP 4739068A1EP-4739068-A1

Abstract

An IC stack includes: a plurality of integrated circuit (IC) structure horizontally separate with each other, wherein each IC structure comprises a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall; wherein the area of the bottom surface or the top surface is larger than that of any sidewall; a laterally extending RDL structure covering each first sidewall of the plurality of IC structures; and an upward extending thermal conductivity layer between two adjacent IC structures; wherein the thermal conductivity of the upward extending thermal conductivity layer is higher than that of Si.

Inventors

  • TONG, HO-MING
  • LU, CHAO-CHUN

Assignees

  • nD-HI Technologies Lab, Inc.
  • Etron Technology, Inc.

Dates

Publication Date
20260506
Application Date
20250224

Claims (20)

  1. An IC stack comprising: a plurality of integrated circuit (IC) structure horizontally separate with each other, wherein each IC structure comprises a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall; wherein the area of the bottom surface or the top surface is larger than that of any sidewall; a laterally extending RDL structure covering each first sidewall of the plurality of IC structures; and an upward extending thermal conductivity layer between two adjacent IC structures; wherein the thermal conductivity of the upward extending thermal conductivity layer is higher than that of Si.
  2. The IC stack of claim 1, further comprising a laterally extending thermal conductivity layer covering each second sidewall of the plurality of IC structures and thermally coupling to the upward extending thermal conductivity layer, wherein the laterally extending RDL structure is opposite to the laterally extending thermal conductivity layer, and the thermal conductivity of the laterally extending thermal conductivity layer is higher than that of Si.
  3. The IC stack of claim 2, wherein the upward extending thermal conductivity layer or the laterally extending thermal conductivity layer comprises BN, AlN, W, SiC or copper.
  4. The IC stack of claim 1, further comprising an upward extending RDL structure covering each third sidewall of the plurality of IC structures, wherein the upward extending RDL structure is electrically connected to the laterally extending RDL structure.
  5. The IC stack of claim 4, wherein each IC structure comprises a DRAM semiconductor die, and the IC stack is an HBM compatible structure.
  6. The IC stack of claim 4, further comprising a logic control chip under and electrically connected to the laterally extending RDL structure of the IC stack.
  7. The IC stack of claim 6, wherein each of the IC structures comprises a DRAM semiconductor die comprising a plurality of memory I/O pads, the logic control chip comprises a plurality of logic I/O pads, and the plurality of memory I/O pads of each DRAM semiconductor die are electrically coupled to the plurality of logic I/O pads through the laterally extending RDL structure.
  8. The IC stack of claim 7, wherein the memory I/O pads do not comprise an electrostatic discharge (ESD) protection circuit, or each DRAM semiconductor die further comprises a plurality of row address pads and a plurality of column address pads physically independent of the plurality of row address pads.
  9. The IC stack of claim 7, wherein each DRAM semiconductor die further comprises a plurality of external bidirectional repeaters, wherein a bidirectional repeater of a second DRAM semiconductor die is electrically coupled to a corresponding bidirectional repeater of a first DRAM semiconductor die through a second metal line of the laterally extending RDL structure or the upward extending RDL structure, and the corresponding bidirectional repeater of the first DRAM semiconductor die is electrically coupled to a corresponding logic I/O pad of the logic control chip through a first metal line of the laterally extending RDL structure or the upward extending RDL structure.
  10. The IC stack of claim 7, wherein each DRAM semiconductor die further comprises a plurality of external bidirectional repeaters, wherein a bidirectional repeater of a first DRAM semiconductor die is electrically coupled to a corresponding a corresponding logic I/O pad of the logic control chip through a first metal line of the laterally extending RDL structure or the upward extending RDL structure, and a bidirectional repeater of a second DRAM semiconductor die is electrically coupled to the corresponding logic I/O pad of the logic control chip through a second metal line of the laterally extending RDL structure or the upward extending RDL structure.
  11. The IC stack of Claim 1, wherein a first IC structure of the plurality of IC structures comprises: a first semiconductor body having a first primary surface and a first secondary surface, with the first primary surface being substantially perpendicular to the first secondary surface; and an interconnection structure including a primary redistribution layer (RDL) over the first primary surface, with the primary RDL having a second secondary surface that is aligned with the first secondary surface of the first semiconductor body; wherein the first secondary surface and the second secondary surface jointly form a secondary plane, wherein the primary RDL further comprises a first conductive element exposed through the second secondary surface of the primary RDL.
  12. The IC stack of Claim 11, wherein the first conductive element comprises a conductive pad on a surface of the primary RDL structure substantially parallel to the first primary surface, a conductive via connecting adjacent layers of the primary RDL, a stacked via traversing the primary RDL, or a combination thereof
  13. The IC stack of Claim 12, wherein the first semiconductor body further includes at least a through-silicon via, a through-molding via, or an insulating element exposed through the first secondary surface.
  14. The IC stack of Claim 11, wherein the first semiconductor body comprises multiple first dies placed in a same package layer, vertically stacked second dies, the vertically stacked second dies placed side-by-side with other third dies in the same package layer, or a combination thereof.
  15. The IC stack of Claim 14, wherein the first semiconductor body comprises a plurality of conductive vias, pillars or plugs of same or different lengths, electrically connecting the multiple first dies to the primary RDL and/or the laterally extending RDL structure.
  16. The IC stack of Claim 11, wherein the laterally extending RDL structure is electrically connected to the first conductive element of the primary RDL, to conductive vias, pillars or plugs in the first semiconductor body, or to a combination thereof; wherein the laterally extending RDL structure includes a hybrid bonding layer or a bump pad array.
  17. An IC stack comprising: a plurality of integrated circuit (IC) structure horizontally separate with each other, wherein each IC structure comprises a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall; wherein the area of the bottom surface or the top surface is larger than that of any of the four sidewalls; a set of upward extending thermal conductivity layers, wherein a corresponding upward extending thermal conductivity layer is disposed between any two adjacent IC structures of the plurality of IC structures; and a first laterally extending thermal conductivity layer covering each second sidewall of the plurality of IC structures and thermally coupling to the set of upward extending thermal conductivity layers; wherein the thermal conductivity of any upward extending thermal conductivity layer and/or the laterally extending thermal conductivity layer is higher than that of Si.
  18. The IC stack of claim 17, further comprises a laterally extending RDL structure covering each first sidewall of the plurality of IC structures.
  19. The IC stack of claim 18, wherein each IC structure comprises a DRAM semiconductor die, and the IC stack further comprises a logic control chip under and electrically connected to the laterally extending RDL structure of the IC stack; wherein the IC stack is an HBM compatible structure.
  20. The IC stack of claim 17, further comprising a second laterally extending thermal conductivity layer covering each third sidewall of the plurality of IC structures, wherein the second laterally extending thermal conductivity layer is thermally coupling to the set of upward extending thermal conductivity layers.

Description

FIELD This disclosure relates in general to a semiconductor device and a method of forming the same, and more particularly to a semiconductor device with side edge interconnection and a method of forming the same. BACKGROUND Tremendous progress has been made in two dimensional (2D) geometrical scaling of conventional transistors due to the great feats of engineering and material science involving extremely complex multiple-step lithographic patterning, new strain enhancing materials and metal oxide gate. However, 2D device scaling is losing momentum as the abovementioned techniques approach their practical limits. Three-dimensional integrated circuit (3D IC) integration which represents a radical departure from the traditional 2D IC integration has been recognized as a next-generation semiconductor technology to simultaneously achieve high performance, low power consumption, small physical size and high integration density. The 3D ICs provide a path to continually meet performance and cost demands of next generation devices while still permitting more relaxed gate lengths with less process complexity for high-end applications such as high-performance computing (HPC), data centers and artificial intelligence (AI). 3D IC integration can proceed via monolithic integration, and/orvertical integration of disparate dies. 3D monolithic integration involves typically vertical integration of multiple active silicon layers with vertical interconnects between the layers. Recently, a "cache-on-central processing unit (CPU)" 3D IC structure has been demonstrated and commercialized using copper hybrid bonding. Today, high-bandwidth-memory (HBM) dynamic random-access memory (DRAM) stacks, each of which created by vertically integrating a number of DRAM dies on a control IC, represent the highest volume commercial 3D ICs today. These HBM DRAM stacks are typically mounted side-by-side with a processor IC on a silicon interposer in 2.5D IC packaging (FIG. 1A) for high-end applications such as HPC, data centers and AI. A 2.5D IC typically contains through- silicon vias (TSVs) in active dies such as DRAM and control ICs, and in the silicon interposer which can be passive or active. A 2.5D IC can also contain redistribution layers (RDLs) in the interposer and active dies. Take ChatGPT for instance, it is powered by nVidia's H100 GPU in 2.5D IC configuration. Going forward, 3D ICs can enable memory on memory, memory over logic, and logic over logic structures using interconnect technologies including TSVs, RDLs containing interconnect wiring and micro-vias, flip chip bonding based on copper pillar micro-bumps or solder bumps, as well as the newly emerged technique of copper hybrid bonding. 3D ICs created by monolithic integration and/or heterogeneous integration allow for vertical stacking of heterogeneous dies and/or active silicon layers from different manufacturing processes and nodes, chip/chiplet reuse, and chiplets-in-SiP (system-in-a-package). Ultimately, 3D IC integration will enable stacking of HBM DRAM stacks on processors to greatly shorten the time of data transfer between DRAM dies and the processor and greatly reduce the peak compute memory bandwidth gap. 3D ICs are ideal for applications that require integration of more transistors in a given footprint (such as mobile system-on-chip, SoC) or for applications already pushing the capability limit of a single die at the most-advanced node, such as HPC, data centers, AI /machine learning, 5G/6G networks, graphics, smartphones/wearables, automotive and others that demand ultra-high-performance, higher-power-efficiency devices. These devices include CPU, GPU (graphics processing unit), FPGA (field-programmable gate array), ASIC (application-specific IC), TPU (tensor processing unit), integrated photonics, AP (application processor for cell phones), packet buffer/router devices, and the like. To accelerate adoption, 3D IC systems must be designed in a holistic manner via IC-package-system co-design, which involves a silicon IP, ICs/chiplets and an IC package, and addresses accompanying power and thermal challenges. In contrast to PPAC (performance, power, area and cost) optimization per square centimeter as applied in 2D packaging, IC-package-system co-design for 3D ICs aims to achieve "PPAC optimization per cubic millimeter", wherein a vertical dimension that covers ICs, interposer, IC package substrate, IC package and system printed circuit board (PCB) must all be considered in all tradeoff decisions. Today, all 3D ICs adopt packaging topologies with single-sided areal electrical interconnects, for instance, from the bottom-side of the control IC in the HBM DRAM stack, which is connected to an interposer, to DRAM dies on top of the control IC, or from the laminate substrate to the bottom side of the CPU in cache-on-CPU. In powering 3D ICs that rely on single-sided interconnects, designers must consider all stacked layers while designing a power delivery network with a