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EP-4739069-A2 - PACKAGING SUBSTRATE

EP4739069A2EP 4739069 A2EP4739069 A2EP 4739069A2EP-4739069-A2

Abstract

A packaging substrate according to the embodiment comprises: a glass core; a wiring layer; and an insulating layer. A measurement point is a point on the surface of the packaging substrate, and ten different measurement points are disposed on the surface. The measurement points are spaced apart by at least 0.05 times the surface length. Er is a value of extreme surface reduced modulus (unit: GPa) measured at the measurement point using a nanoindentation method, Er_av is the average of the extreme surface reduced modulus values measured at the measurement points, and Er_stdev is the standard deviation thereof. The ratio of Er_stdev to Er_av may be 7% or less. The packaging substrate according to the embodiment can reduce overall stress by adjusting variations in the extreme surface modulus according to in-plane location within a certain range.

Inventors

  • KIM, SUNGJIN
  • KIM, JINCHEOL

Assignees

  • Absolics Inc.

Dates

Publication Date
20260506
Application Date
20251028

Claims (15)

  1. A packaging substrate comprising: a glass core; a wiring layer; and an insulating layer, wherein the glass core is a plate-shaped glass in which vias are disposed, the wiring layer is an electrically conductive layer disposed on a surface of the glass core, the insulating layer is a layer disposed in a space between the electrically conductive layers and comprises a mixture of a polymer resin and insulating particles, the packaging substrate has an upper surface on which an electronic device is mounted and a lower surface facing the upper surface, a measurement point is a point on the surface of the packaging substrate, ten measurement points, each different from one another, are disposed on the surface, the measurement points are spaced apart by at least 0.05 times the surface length of the substrate, Er is a value of extreme surface reduced modulus (unit: GPa) measured at the measurement point using a nanoindentation method, Er_av is an average of the extreme surface reduced modulus values measured at the measurement points, Er_stdev is a standard deviation of the extreme surface reduced modulus values measured at the measurement points, the measurement is performed at 27°C, and a ratio of Er_stdev to Er_av, based on the overall Er_av, is 7% or less.
  2. The packaging substrate of claim 1, wherein Er_av is 20 GPa or less, and wherein Er_stdev is 1 GPa or less.
  3. The packaging substrate of claim 1 or claim 2, wherein an insulating layer disposed above the glass core is an upper insulating layer, a cover layer is further disposed on the upper insulating layer, the cover layer is a polymer resin or an inorganic insulating layer, the surface is an exposed surface of the cover layer, and the maximum Er value among the Er values of the cover layer is 16 GPa or less.
  4. The packaging substrate of any one of claim 1 to claim 3, wherein an insulating layer disposed below the glass core is a lower insulating layer, a solder resist layer is further disposed below the lower insulating layer, the surface is an exposed surface of the solder resist layer, and the maximum Er value among the Er values of the solder resist layer is 21 GPa.
  5. The packaging substrate of any one of claim 1 to claim 4, an average storage modulus (E') at a temperature of 20°C to less than 30°C is referred to as E'20, an average storage modulus (E') at a temperature of 140°C to less than 150°C is referred to as E'140, and E'20 - E'140 of the packaging substrate is 80 MPa or less.
  6. The packaging substrate of any one of claim 1 to claim 5, wherein a loss modulus (E") of the packaging substrate at 30°C is 5 MPa or more.
  7. The packaging substrate of any one of claim 1 to claim 6, wherein an extreme surface hardness (HIT), measured at any point on an upper or lower surface of the packaging substrate, is less than 1 GPa.
  8. The packaging substrate of any one of claim 1 to claim 7, wherein a contact compliance of the packaging substrate is 12 nm/mN or less.
  9. The packaging substrate of any one of claim 1 to claim 8, wherein an insulating layer disposed on an upper portion of the glass core is an upper insulating layer, a cover layer is further disposed on an upper portion of the upper insulating layer, the cover layer comprises a polymer resin or an insulating inorganic layer, an insulating layer disposed on a lower portion of the glass core is a lower insulating layer, a solder resist layer is further disposed below the lower insulating layer, and extreme surface hardnesses (HITs) of the cover layer and the solder resist layer are both 0.3 GPa or more.
  10. The packaging substrate of claim 9, wherein an extreme surface hardness (HIT) of the solder resist layer is greater than an extreme surface hardness (HIT) of the cover layer.
  11. The packaging substrate of claim 9, wherein an extreme surface hardness (HIT) of the solder resist layer is 0.8 GPa or more.
  12. The packaging substrate of any one of claim 1 to claim 11, wherein a measurement point is a point on a surface of the packaging substrate, ten distinct measurement points are disposed on the surface, the measurement points are spaced apart by at least 0.05 times a diameter or diagonal length of the packaging substrate, HIT is an extreme surface hardness (unit: GPa) measured at the measurement point using a nanoindentation method, HIT_stdev is a standard deviation of the extreme surface hardness values measured at the measurement points, and the HIT_stdev is 0.1 GPa or less.
  13. The packaging substrate of any one of claim 1 to claim 12, wherein a difference between the maximum and minimum Er values measured at the respective measurement points is 4 GPa or less.
  14. The packaging substrate of any one of claim 1 to claim 13, wherein the surface is an exposed surface of the insulating layer, and the maximum Er value among the Er values of the insulating layer is 22 GPa or less.
  15. The packaging substrate of any one of claim 1 to claim 14, wherein a tan delta value of the packaging substrate at 30°C is 0.009 or less.

Description

This application claims priorities of U.S. Provisional Patent Application No. 63/714,151 and, filed on October 31, 2024, and U.S. Provisional Patent Application No. 63/714,153, filed on October 31, 2024. BACKGROUND TECHNICAL FIELD The embodiment relates to a packaging substrate in which properties such as extreme surface reduced modulus are controlled. The embodiment relates to a packaging substrate having controlled loss modulus, hardness, and the like. DESCRIPTION OF RELATED ART In the manufacturing of electronic components, the process of forming circuits on a semiconductor wafer is referred to as a front-end (FE) process, and the process of assembling the wafer into a state usable in actual products is referred to as a back-end (BE) process, wherein a packaging process is included in the back-end process. The four core technologies of the semiconductor industry, which have enabled the rapid development of electronic products in recent years, are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Although semiconductor technology has advanced in various forms such as sub-micron or nanometer-scale line widths, integration of more than ten million cells, high-speed operation, and significant heat generation, the technology to perfectly package such devices has not been sufficiently established. Accordingly, the electrical performance of a semiconductor may be determined not by the performance of the semiconductor technology itself, but by the packaging technology and the resulting electrical connection. Materials used for packaging substrates include ceramics or resins. In the case of ceramic substrates, due to their high resistivity or high dielectric constant, it is not easy to mount high-performance, high-frequency semiconductor elements. In the case of resin substrates, although high-performance, high-frequency semiconductor elements can be mounted relatively easily, there are limitations in reducing the wiring pitch. Recently, studies applying glass substrates as high-end packaging substrates have been conducted. By forming through-holes in a glass substrate and applying conductive material in the through-holes, the wiring length between the device and the motherboard can be shortened, and excellent electrical characteristics can be obtained. Related arts include Korean Patent Publication No. 10-2020-0030430 and Korean Patent Publication No. 10-2023-0145447. SUMMARY In some embodiments, a packaging substrate with improved reliability by controlling properties such as extreme surface reduced modulus is provided. In some embodiments, a packaging substrate in which the loss modulus, hardness, and the like are simultaneously controlled is provided. According to the embodiments, a packaging substrate includes: a glass core, a wiring layer, and an insulating layer. The glass core is a plate-shaped glass in which vias are arranged, the wiring layer is an electrically conductive layer disposed on a surface of the glass core, and the insulating layer is a layer disposed in the spaces between the electrically conductive layers and includes a mixture of a polymer resin and insulating particles. The packaging substrate has a top surface on which an electronic component is mounted and a bottom surface opposite thereto. A measurement point is a point on the surface of the packaging substrate, and ten measurement points are arranged on the surface with each having a spacing of at least 0.05 times the total surface length from each other. The measurement is performed at 27°C. Er is the value of extreme surface reduced modulus (unit: GPa) measured at each measurement point using a nanoindentation method. Er_av is the average of the extreme surface reduced modulus values measured at the measurement points. Er_stdev is the standard deviation of the extreme surface reduced modulus values measured at the measurement points. The packaging substrate may have a ratio of Er_stdev to Er_av of 7% or less. The difference between the maximum and minimum Er values among those measured at the individual measurement points may be 4 GPa or less. The surface is the exposed surface of the insulating layer, and the maximum Er value of the insulating layer may be 22 GPa or less. The insulating layer disposed above the glass core is an upper insulating layer, and a cover layer may be further disposed on the upper insulating layer. The cover layer may be a polymer resin layer or an insulating inorganic layer. The surface is the exposed surface of the cover layer, and the maximum Er value of the cover layer may be 16 GPa or less. The insulating layer disposed below the glass core is a lower insulating layer, and a solder resist layer may be further disposed below the lower insulating layer. The surface is the exposed surface of the solder resist layer, and the maximum Er value of the solder resist layer may be 21 GPa or less. The Er_stdev of the packaging substrate may be