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EP-4739070-A1 - PACKAGING SUBSTRATE

EP4739070A1EP 4739070 A1EP4739070 A1EP 4739070A1EP-4739070-A1

Abstract

An embodiment relates to a packaging substrate comprises: a glass core; a wiring layer; and an insulating layer, wherein the glass core is a plate-shaped glass in which vias are disposed, the wiring layer is an electrically conductive layer disposed on a surface of the glass core, the insulating layer is a layer disposed in a space between the electrically conductive layers and comprising a mixture of a polymer resin and an insulating filler, the packaging substrate has an upper surface on which a semiconductor element is mounted and a lower surface facing the upper surface, the insulating layer disposed on an upper portion of the glass core is an upper insulating layer, a cover layer is further disposed on the upper insulating layer, the insulating layer disposed on a lower portion of the glass core is a lower insulating layer, and a solder resist layer is further disposed on the lower insulating layer.

Inventors

  • KIM, SUNGJIN
  • KIM, JINCHEOL

Assignees

  • Absolics Inc.

Dates

Publication Date
20260506
Application Date
20251008

Claims (10)

  1. A packaging substrate comprising: a glass core; a wiring layer; and an insulating layer, wherein the glass core is a plate-shaped glass in which vias are disposed, the wiring layer is an electrically conductive layer disposed on a surface of the glass core, the insulating layer is a layer disposed in a space between the electrically conductive layers and comprising a mixture of a polymer resin and insulating particles, the packaging substrate has an upper surface on which a semiconductor element is mounted and a lower surface facing the upper surface, the insulating layer disposed on an upper portion of the glass core is an upper insulating layer, a cover layer is further disposed on the upper insulating layer, the insulating layer disposed on a lower portion of the glass core is a lower insulating layer, a solder resist layer is further disposed on the lower portion of the lower insulating layer, a flexibility index FI is a value represented by Equation 1 below, and the FI of the cover layer is greater than the FI of the solder resist layer: FI = 10 , 000 × E ′ × tan δ / H × Er wherein, in Equation 1, E' denotes a storage modulus (GPa), tan δ denotes a loss tangent, H denotes a hardness (GPa), and Er denotes a reduced modulus (GPa).
  2. The packaging substrate according to claim 1, wherein the FI of the cover layer is in a range of 7.5 or more and 8.3 or less.
  3. The packaging substrate according to claim 1 or claim 2, wherein the FI of the solder resist layer is in a range of 3.9 or more and 4.6 or less.
  4. The packaging substrate according to anyone from claim 1 to claim 3, wherein a storage modulus (E') of the packaging substrate is in a range of 0.73 GPa or more and 0.85 GPa or less.
  5. The packaging substrate according to anyone from claim 1 to claim 4, wherein a loss tangent (tan δ) of the packaging substrate is in a range of 0.0080 or more and 0.0090 or less.
  6. The packaging substrate according to anyone from claim 1 to claim 5, wherein a hardness (H) of the cover layer is in a range of 0.55 GPa or more and 0.65 GPa or less.
  7. The packaging substrate according to anyone from claim 1 to claim 6, wherein a hardness (H) of the solder resist layer is in a range of 0.82 GPa or more and 0.93 GPa or less.
  8. The packaging substrate according to anyone from claim 1 to claim 7, wherein a reduced modulus (Er) of the cover layer is in a range of 13.5 GPa or more and 15.0 GPa or less.
  9. The packaging substrate according to anyone from claim 1 to claim 8, wherein a reduced modulus (Er) of the solder resist layer is in a range of 17.8 GPa or more and 19.6 GPa or less.
  10. The packaging substrate according to anyone from claim 1 to claim 9, wherein a difference between the FI of the cover layer and the FI of the solder resist layer is in a range of 3.6 or more and 4.2 or less.

Description

This application claims the priority of U.S. Provisional Patent Application No. 63/714,154, filed October 31, 2024. BACKGROUND Technical Field An embodiment relates to a packaging substrate in which the difference in physical properties between the upper and lower portions of a glass core is adjusted, improving thermal shock resistance, impact resistance, durability, reliability, etc. In the manufacture of electronic components, implementing a circuit on a semiconductor wafer is referred to as a front-end (FE) process, and assembling the wafer into a state in which it can be used in an actual product is referred to as a back-end (BE) process, in which a packaging process is included. Four core technologies of the semiconductor industry that have enabled the rapid advancement of electronic products in recent years comprise semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved in various forms, such as a line width at the sub-micrometer or nanometer level, more than ten million cells, high-speed operation, and high heat dissipation. However, the technology for perfectly packaging such semiconductors has not kept pace. Accordingly, the electrical performance of a semiconductor may be determined by the packaging technology and the electrical connection therefrom rather than by the performance of the semiconductor technology itself. As materials for packaging substrates, ceramics or resins are applied. In the case of ceramic substrates, their high resistance or high dielectric constant makes it difficult to mount high-performance, high-frequency semiconductor elements thereon. In the case of resin substrates, it is relatively possible to mount high-performance, high-frequency semiconductor elements; however, there is a limitation in reducing the wiring pitch. Recently, research has been underway to apply glass substrates for high-end packaging substrates. By forming through holes in a glass substrate and applying a conductive material to the through holes, the wiring length between the element and the motherboard may be shortened, and excellent electrical characteristics may be achieved. Related arts include Korean Patent Publication No. 10-2020-0030430 and Korean Patent Publication No. 10-2023-0145447. SUMMARY In some embodiments, a packaging substrate in which a difference in physical properties between an upper portion and a lower portion of a glass core is adjusted, thereby improving thermal shock resistance, impact resistance, durability, reliability, etc., is disposed. According to an embodiment, a packaging substrate according to one embodiment includes: a glass core; a wiring layer; and an insulating layer, wherein the glass core is a plate-shaped glass in which vias are disposed, the wiring layer is an electrically conductive layer disposed on a surface of the glass core, and the insulating layer is a layer disposed in a space between the electrically conductive layers and containing a mixture of a polymer resin and insulating particles. The packaging substrate has an upper surface on which a semiconductor element is mounted and a lower surface facing the upper surface. The insulating layer disposed on an upper portion of the glass core is an upper insulating layer, a cover layer is further disposed on the upper insulating layer, the insulating layer disposed on a lower portion of the glass core is a lower insulating layer, and a solder resist layer is further disposed on the lower insulating layer. A flexibility index (FI) is a value represented by Equation 1 below. FI=10,000×E′×tanδ/H×Er In Equation 1, E' denotes a storage modulus (GPa), tan δ denotes a loss tangent, H denotes a hardness (GPa), and Er denotes a reduced modulus (GPa). The FI of the cover layer is greater than the FI of the solder resist layer. The FI of the cover layer may be 7.5 or more and 8.3 or less. The FI of the solder resist layer may be 3.9 or more and 4.6 or less. The storage modulus (E') of the packaging substrate may be 0.73 GPa or more and 0.85 GPa or less. The loss tangent (tan δ) of the packaging substrate may be 0.0080 or more and 0.0090 or less. The hardness (H) of the cover layer may be 0.55 GPa or more and 0.65 GPa or less. The hardness (H) of the solder resist layer may be 0.82 GPa or more and 0.93 GPa or less. The reduced modulus (Er) of the cover layer may be 13.5 GPa or more and 15.0 GPa or less. The reduced modulus (Er) of the solder resist layer may be 17.8 GPa or more and 19.6 GPa or less. A difference between the FI of the cover layer and the FI of the solder resist layer may be 3.6 or more and 4.2 or less. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view of a packaging substrate on which a semiconductor element manufactured according to an embodiment is mounted.FIG. 2 is a conceptual cross-sectional view taken along line A-A' of FIG. 1.FIG. 3 is a conceptual cross-sectional view illustrating a cross sect