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EP-4739072-A1 - PACKAGING SUBSTRATE

EP4739072A1EP 4739072 A1EP4739072 A1EP 4739072A1EP-4739072-A1

Abstract

The embodiment relates to a packaging substrate comprising: a glass wafer 20; a plurality of vias 25 disposed in the glass wafer 20; copper electrodes 40 disposed on the vias 25 or on the surface of the glass wafer 20; and an insulating layer 30 surrounding the vias 25 or the copper electrodes 40. The packaging substrate 100 comprises P and Zn as eluted impurities, and the content of the eluted impurities is based on an analysis value obtained by preparing an analytical solution through pretreatment at 200°C for 16 hours in a graphite block after adding 70 mol% nitric acid to the packaging substrate 100, and analyzing the solution using an ICP-MS device (Nexlon2000 model manufactured by PerkinElmer) in accordance with KS M 0025:2008 test method. The content of P (by weight) is 1,500 ppb or less, and the content of Zn (by weight) is 500 ppb or less.

Inventors

  • KIM, SUNGJIN
  • KIM, JINCHEOL

Assignees

  • Absolics Inc.

Dates

Publication Date
20260506
Application Date
20251023

Claims (10)

  1. A packaging substrate comprising: a glass wafer; a plurality of vias disposed in the glass wafer; copper electrodes disposed on the vias or on the surface of the glass wafer; and an insulating layer surrounding the vias or the copper electrodes, wherein the packaging substrate comprises P and Zn as eluted impurities, wherein the content of the eluted impurities is based on an analysis value obtained by preparing an analytical solution through pretreatment for 16 hours at 200°C in a graphite block after adding 70 mol% nitric acid to the packaging substrate, and analyzing the solution using an ICP (inductively coupled plasma)-MS device (Nexlon2000 model manufactured by PerkinElmer) in accordance with KS M 0025:2008 test method, wherein the content of P (by weight) is 1,500 ppb or less, and wherein the content of Zn (by weight) is 500 ppb or less.
  2. The packaging substrate of claim 1, wherein a seed layer is further comprised beneath the copper electrodes, wherein the seed layer comprises copper and titanium, wherein the insulating layer comprises a polymer resin and inorganic particles, wherein the inorganic particles comprise silica, and wherein the polymer resin comprises at least one selected from the group consisting of epoxy resin, acrylic resin, urethane resin, and combinations thereof.
  3. The packaging substrate of claim 1 or claim 2, wherein the packaging substrate has a polyhedral shape overall, and wherein 2 to 4 faces among the six faces of the polyhedron expose cut surfaces.
  4. The packaging substrate of any one from claim 1 to claim 3, wherein the glass wafer is a borosilicate-based plate glass.
  5. The packaging substrate of claim 4, wherein the eluted impurities further comprise Si and B, and wherein the weight ratio of the content of Si to B is in the range of 1:5 to 7.
  6. The packaging substrate of claim 4 or claim 5, wherein the analysis value of the eluted impurities comprises the intensities of B and F, and wherein the intensity ratio of the F peak based on the B peak is 50 or less.
  7. The packaging substrate of any one from claim 4 to claim 6, wherein the eluted impurities further comprise B and Ti, and wherein the weight ratio of the content of B to Ti is in the range of 1:50 to 70.
  8. The packaging substrate of any one from claim 1 to claim 7, wherein the eluted impurities further comprise Al, and wherein the content of Al (by weight) is 900 ppb or less.
  9. The packaging substrate of any one from claim 1 to claim 8, wherein the eluted impurities further comprise B, and wherein the weight ratio of the content of B to Zn is in the range of 1:2 to 5.
  10. The packaging substrate of any one from claim 1 to claim 9, wherein the weight ratio of the content of B to P is in the range of 1:5 to 30.

Description

This application claims priority of U.S. Provisional Patent Application No. 63/713,080, filed on October 29, 2024. BACKGROUND TECHNICAL FIELD The embodiment relates to a packaging substrate and the like. DESCRIPTION OF RELATED ART In the manufacture of electronic components, the process of forming circuits on a semiconductor wafer is generally called the front-end (FE) process, whereas assembling the processed wafer into a form suitable for end products is known as the back-end (BE) process. The packaging operation is comprised in the back-end process. The four pillars that have propelled the rapid progress of modern electronic products are semiconductor technology, semiconductor packaging technology, manufacturing-process technology, and software. Although semiconductor technology has achieved sub-micron line widths, tens of millions of transistors, high-speed operation, and substantial heat dissipation, the packaging technologies required to fully support these advances have not evolved at the same pace. Consequently, a semiconductor device's overall electrical performance is often dictated more by its packaging and electrical interconnects than by the device's intrinsic characteristics. Materials commonly used for packaging substrates include ceramics and resins. Ceramic substrates-for example, silicon-based ceramics-exhibit high resistivity and high dielectric constants, which renders them less suitable for mounting high-performance, high-frequency semiconductor devices. Resin substrates, on the other hand, can accommodate such high-performance, high-frequency devices, but they offer limited capability for reducing the wiring pitch. Glass substrates have recently emerged as promising candidates for high-end packaging. By forming through-vias in the glass and filling them with conductive material, the interconnect path between the semiconductor device and the motherboard can be shortened, thereby enabling superior electrical performance. Related art includes Korean Patent Publication No. 10-2023-0038664. SUMMARY In some embodiments, a packaging substrate, and a method for manufacturing it, in which the impurity content is reduced is provided. According to the embodiments, a packaging substrate according to an embodiment includes: a glass wafer; a plurality of vias disposed in the glass wafer; copper electrodes disposed on the vias or on the surface of the glass wafer; and an insulating layer surrounding the vias or the copper electrodes. The packaging substrate comprises P and Zn as eluted impurities. The content of the eluted impurities is determined by preparing an analytical solution in which 70 mol% nitric acid is added to the packaging substrate and pretreated in a graphite block at 200°C for 16 hours, and analyzing the analytical solution using an ICP (inductively coupled plasma)-MS device (Nexlon2000 model manufactured by PerkinElmer) in accordance with KS M 0025:2008 test method. The content of P (by weight) may be 1,500 ppb or less. The content of Zn (by weight) may be 500 ppb or less. A seed layer may further be disposed beneath the copper electrodes. The seed layer may include copper and titanium. The insulating layer may include a polymer resin and inorganic particles. The inorganic particles may include silica. The polymer resin may include at least one selected from the group consisting of epoxy resin, acrylic resin, urethane resin, and combinations thereof. The packaging substrate may have a polyhedral shape overall. Two to four faces among the six faces of the polyhedron may expose cut surfaces. The glass wafer may include borosilicate-based plate glass. The eluted impurities may further include Si and B. The weight ratio of Si to B may be in the range of 1:5 to 7. The analysis of eluted impurities may include the intensity of B and the intensity of F. The intensity ratio of the F peak based on the B peak may be 50 or less. The eluted impurities may further include B and Ti. The weight ratio of B to Ti may be in the range of 1:50 to 70. The eluted impurities may further include Al. The content of Al (by weight) may be 900 ppb or less. The eluted impurities may further include B. The weight ratio of B to Zn may be in the range of 1:2 to 5.. The weight ratio of B to P may be in the range of 1:5 to 30. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view illustrating the structure of a packaging substrate according to an embodiment. DESCRIPTION OF THE EMBODIMENTS The following embodiments are explained in detail with reference to the accompanying drawings, so that those skilled in the art may readily practice the invention. Nevertheless, the invention may be embodied in various forms and is not confined to the specific examples provided herein. Throughout the specification, like reference numerals indicate like elements. In this specification, the phrase "combinations thereof," when used in a Markush grouping, refers to any mixture or combination containing at least o