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EP-4739074-A1 - METHODS AND APPARATUS TO REDUCE CRACKING IN GLASS CORES

EP4739074A1EP 4739074 A1EP4739074 A1EP 4739074A1EP-4739074-A1

Abstract

Methods and apparatus to reduce cracking in glass cores are disclosed. An example apparatus includes a package substrate comprising a glass core having an opening extending between first and second surfaces of the glass core, the first surface opposite the second surface, and a conductive material, a first portion of the conductive material within the opening, a second portion of the conductive material protruding beyond the first surface of the glass core, a first surface of the first portion in continuity with a second surface of the second portion.

Inventors

  • RAMANUJA PIETAMBARAM, SRINIVAS VENKATA
  • IBRAHIM, TAREK
  • TANIKELLA, RAVINDRA

Assignees

  • Intel Corporation

Dates

Publication Date
20260506
Application Date
20250710

Claims (15)

  1. An apparatus comprising: a glass core having an opening extending between first and second surfaces of the glass core, the first surface opposite the second surface; and a conductive material, a first portion of the conductive material within the opening, a second portion of the conductive material protruding beyond the first surface of the glass core, a first surface of the first portion in continuity with a second surface of the second portion.
  2. The apparatus of claim 1, wherein the second surface is substantially parallel to an inner wall of the opening.
  3. The apparatus of any one of claims 1-2, wherein the second portion of the conductive material protrudes beyond the first surface of the glass core by at least 3 micrometers.
  4. The apparatus of any one of claim 1-3, wherein the first surface of the first portion is a first radial distance from a longitudinal axis of the opening and the second surface of the second portion is a second radial distance from the longitudinal axis, the second radial distance substantially equal to the first radial distance.
  5. The apparatus of any one of claims 1-4, further including a dielectric layer adjacent the first surface of the glass core, the dielectric layer to laterally surround the second portion of the conductive material.
  6. The apparatus of claim 5, further including a conductive pad on an outward facing surface of the dielectric layer, the second portion of the conductive material to extend a full distance through a thickness of the dielectric layer to electrically couple with the conductive pad.
  7. The apparatus of any one of claims 5-6, further including a layer of material between the dielectric layer and the first surface of the glass core and between the second portion of the conductive material and the dielectric layer, the layer of material including silicon and nitrogen.
  8. The apparatus of any one of claims 5-7, further including: a conductive pad on an outward facing surface of the dielectric layer; and a metal via extending through the dielectric layer, the metal via electrically coupling the second portion of the conductive material to the conductive pad.
  9. The apparatus of claim 8, wherein the metal via includes a first width and the second portion includes a second width greater than the first width.
  10. The apparatus of any one of claims 1-9, further including a seed layer along an inner wall of the opening, the seed layer between the glass core and the conductive material.
  11. The apparatus of claim 10, wherein the seed layer is absent along the first and second surfaces of the glass core.
  12. The apparatus of any one of claims 10-11, wherein the seed layer extends along the second portion of the conductive material beyond the first surface of the glass core.
  13. The apparatus of any one of claims 1-12, wherein the first and second portions of the conductive material correspond to first and second portions of an elongate shaft, the elongate shaft having a length greater than a thickness of the glass core such that the second portion of the elongate shaft is positioned outside the glass core.
  14. The apparatus of claim 13, further including a buffer layer in contact with the glass core and the second portion of the elongate shaft.
  15. The apparatus of any one of claims 13-14, wherein the elongate shaft includes opposing ends separated from the glass core, the second portion of the elongate shaft including a first one of the opposing ends, the apparatus further including a dielectric including silicon and nitrogen, the dielectric in contact with the first one of the opposing ends of the elongate shaft and the glass core.

Description

BACKGROUND In many electronic devices, integrated circuit (IC) chips and/or semiconductor dies are connected to larger circuit boards such as motherboards and/or other types of printed circuit boards (PCBs) via a package substrate. Some package substrates include a glass substrate (e.g., a glass core) having one or more vias extending between first and second sides of the glass substrate. Conductive material may be provided in the vias to electrically couple devices (e.g., the IC chips and/or semiconductor dies) to each other and/or to a PCB. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an example integrated circuit (IC) package constructed in accordance with teachings disclosed herein.FIG. 2A is an example first package substrate constructed in accordance with teachings disclosed herein.FIG. 2B is a detailed view of a portion of the example first package substrate of FIG. 2A.FIG. 3A is an example second package substrate constructed in accordance with teachings disclosed herein.FIG. 3B is a detailed view of a portion of the example second package substrate of FIG. 3A.FIG. 4 is a flowchart representative of an example method of manufacturing the example first package substrate of FIGS. 2A and 2B and/or the example second package substrate of FIGS. 3A and 3B in accordance with example techniques described in connection with FIGS. 5A-6C.FIGS. 5A-5J illustrate various stages in an example process of fabrication of the example first package substrate of FIGS. 2A and 2B.FIGS. 5A-5F and 6A-6C illustrate various stages in an example process of fabrication of the example second package substrate of FIGS. 3A and 3B.FIG. 7 is a top view of a wafer including dies that may be included in an IC package constructed in accordance with teachings disclosed herein.FIG. 8 is a cross-sectional side view of an IC device that may be included in an IC package constructed in accordance with teachings disclosed herein.FIG. 9 is a cross-sectional side view of an IC device assembly that may include an IC package constructed in accordance with teachings disclosed herein.FIG. 10 is a block diagram of an example electrical device that may include an IC package constructed in accordance with teachings disclosed herein. In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. The figures are not necessarily to scale. Instead, the thickness of the layers or regions may be enlarged in the drawings. Although the figures show layers and regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended, and/or irregular. DETAILED DESCRIPTION FIG. 1 illustrates an example integrated circuit (IC) package 100 constructed in accordance with teachings disclosed herein. In the illustrated example, the IC package 100 is electrically coupled to an underlying substrate 102 via an array of contacts 104 on a package mounting surface 106 (e.g., a bottom surface, an external surface) of the package. In some examples, the substrate 102 can be implemented by a package substrate or a printed circuit board (PCB). In the illustrated example, the contacts 104 are represented as pads or lands. However, in some examples, the IC package 100 may include balls, pins, and/or any other type of contact, in addition to or instead of the pads or lands shown to enable the electrical coupling of the IC package 100 to the substrate 102. In this example, the package 100 includes two semiconductor dies 108, 110 (e.g., silicon dies), sometimes also referred to as chips or chiplets, that are mounted to a package substrate 112 and enclosed by a package lid 114 (e.g., a mold compound, an integrated heat spreader (IHS)). Thus, the package substrate 112 is an example means for supporting a semiconductor die. In some examples, the package lid 114 is omitted, thereby leaving the semiconductor dies 108, 110 exposed or bare. While the example IC package 100 of FIG. 1 includes two dies 108, 110, in other examples, the IC package 100 may have only one die or more than two dies. In some examples, one of the dies 108, 110 (or a separate die) is embedded in the package substrate 112. The dies 108, 110 can provide any suitable type of functionality (e.g., data processing, memory storage, etc.). In some examples, one or both of the dies 108, 110 are implemented by a die package including multiple dies arranged in a stacked formation. For example, the die 110 can include a stack of Dynamic Random Access Memory (DRAM) die arranged on top of a memory controller die to form a memory die stack. As shown in the illustrated example, each of the dies 108, 110 is electrically and mechanically coupled to the package substrate 112 via corresponding arrays of interconnects 116. In FIG. 1, the interconnects are shown as bumps. The interconnects 116 can include solder joints, micro bumps, combinations