EP-4739075-A2 - HIGH BANDWIDTH MEMORY STACK WITH SIDE EDGE INTERCONNECTION AND 3D IC STRUCTURE WITH THE SAME

EP4739075A2EP 4739075 A2EP4739075 A2EP 4739075A2EP-4739075-A2

Abstract

An IC structure includes a memory stack including semiconductor dies horizontally separate with each other, wherein each semiconductor die has a top surface, a bottom surface, four sidewalls, and a plurality of edge pads arranged along a sidewall. The IC structure further includes a memory controller and a processor circuit under the memory stack and electrically connected to the edge pads of each semiconductor die, and a packaging substrate under and electrically connected to the memory controller and processor. There is no interposer between the packaging substrate and the memory controller and the processor circuit, and there is no TSV in each semiconductor die.

Inventors

TONG, HO-MING
LU, CHAO-CHUN

Assignees

nD-HI Technologies Lab, Inc.
Etron Technology, Inc.

Dates

Publication Date: 20260506
Application Date: 20250915

Claims (20)

An IC structure comprising: a memory stack comprising: a plurality of semiconductor dies horizontally separate with each other, wherein each semiconductor die comprises a top surface, a bottom surface opposite to the top surface, and four sidewalls comprising a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads arranged along the first sidewall; wherein the area of the bottom surface or the top surface of each semiconductor die is larger than that of any sidewall; and a logic die with memory controller and processor circuit under the memory stack and electrically connected to the plurality of edge pads of each semiconductor die; and a packaging substrate under and electrically connected to the logic die with memory controller and processor; wherein there is no interposer between the packaging substrate and the logic die with memory controller and processor circuit, and there is no TSV in each semiconductor die.
The IC structure of claim 1, further comprising: an upward extending thermal conductivity layer between two adjacent semiconductor dies; wherein the thermal conductivity of the upward extending thermal conductivity layer is higher than that of Si or SiO 2 ; and/or a laterally extending thermal conductivity layer covering each second sidewall of the plurality of semiconductor dies and thermally coupling to the upward extending thermal conductivity layer, wherein the laterally extending thermal conductivity layer is opposite to the first sidewalls of the plurality of semiconductor dies, and the thermal conductivity of the laterally extending thermal conductivity layer is higher than that of Si or SiO 2 .
The IC structure of claim 2, wherein the upward extending thermal conductivity layer or the laterally extending thermal conductivity layer comprises undoped polysilicon, large crystalline silicon, SiC, BN, AlN, W, or copper.
The IC structure of claim 1, wherein each semiconductor die comprises a DRAM die, and the plurality of edge pads of each DRAM die includes about 128 to 5000 edge pads.
The IC structure of claim 4, wherein the plurality of edge pads of each semiconductor die includes a subset of data pads, and the logic die with memory controller and processor circuit selects a predetermined data width from the subset of data pads of one semiconductor die, or portion of the plurality of semiconductor dies, or all the plurality of semiconductor dies.
The IC structure of claim 5, wherein the predetermined data width selected by the logic die with memory controller and processor circuit is set by a mode register in each semiconductor die.
The IC structure of claim 5, wherein the logic die with memory controller and processor circuit selects the predetermined data width from the subset of data pads of a portion or all of the plurality of semiconductor dies by a cross-bar circuit.
The IC structure of claim 1, wherein the logic die with memory controller and processor circuit includes multiple TSVs.
The IC structure of claim 1, further comprising a heat sink over the logic die with memory controller and processor circuit adjacent to the first memory stack, and a top surface of the heat sink is leveled with that of the first memory stack.
The IC structure of claim 1, further comprising: a second memory stack comprising: a plurality of semiconductor dies horizontally separate with each other, wherein each semiconductor die comprises a top surface, a bottom surface opposite to the top surface, and four sidewalls comprising a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads arranged along the first sidewall; wherein the area of the bottom surface or the top surface of each semiconductor die of the second memory stack is larger than that of any sidewall; and an upward extending thermal conductivity layer between two adjacent semiconductor memory dies; wherein the thermal conductivity of the upward extending thermal conductivity layer is higher than that of Si or SiO 2 ; wherein the first memory stack and the second memory stack are disposed over the logic die with memory control and processor circuit.
The IC structure of claim 1, further comprising: a second memory stack, a third memory stack, and a fourth memory stack, each of them comprising: a plurality of semiconductor dies horizontally separate with each other, wherein each semiconductor die comprises a top surface, a bottom surface opposite to the top surface, and four sidewalls comprising a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads arranged along the first sidewall; wherein the area of the bottom surface or the top surface of each semiconductor die is larger than that of any sidewall; and an upward extending thermal conductivity layer between two adjacent semiconductor memory dies; wherein the thermal conductivity of the upward extending thermal conductivity layer is higher than that of Si or SiO 2 ; wherein the first memory stack, the second memory stack, the third memory stack and the fourth memory stack are disposed over the logic die with memory control and processor circuit, respectively.
An IC structure comprising: a memory stack comprising: a plurality of semiconductor dies horizontally separate with each other, wherein each semiconductor die comprises a top surface, a bottom surface opposite to the top surface, and four sidewalls comprising a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads arranged along the first sidewall; wherein the area of the bottom surface or the top surface of each semiconductor die is larger than that of any sidewall; and an upward extending thermal conductivity layer between two adjacent semiconductor memory dies, wherein the thermal conductivity of the upward extending thermal conductivity layer is higher than that of Si or SiO 2 ;a logic die with memory controller and processor circuit horizontally spaced apart from the memory stack; and a packaging substrate under the memory stack and the logic die with memory controller and processor circuit, wherein the packaging substrate comprises an embedded multi-die interconnect bridge (EMIB) structure electrically connected to the memory stack and the logic die with memory controller and processor circuit, wherein there is no interposer between the packaging substrate and the logic die with memory controller and processor circuit, and there is no TSV in each semiconductor die.
The IC structure of claim 12, further comprising a laterally extending thermal conductivity layer covering each second sidewall of the plurality of semiconductor dies and thermally coupling to the upward extending thermal conductivity layer, wherein the laterally extending thermal conductivity layer is opposite to the first sidewalls of the plurality of semiconductor dies, and the thermal conductivity of the laterally extending thermal conductivity layer is higher than that of Si or SiO 2 .
The IC structure of claim 12, wherein each semiconductor die comprises a DRAM die, and the plurality of edge pads of each DRAM die includes about 128 to 5000 edge pads.
The IC structure of claim 12, wherein the logic die with memory controller and processor circuit includes multiple TSVs.
The IC structure of claim 12, wherein each edge pad of each semiconductor die includes an edge contact in a back-end-of-line (BEOL) region and a conductive via over the edge contact and in a dielectric layer at the top surface, wherein the area of the conductive via is greater than that of the edge contact.
The IC structure of claim 12, wherein each edge pad of each semiconductor die includes an edge contact in a back-end-of-line (BEOL) region and a conductive via over the edge contact and in a redistribution layer (RDL) at the top surface, wherein the area of the conductive via is greater than that of the edge contact.
The IC structure of claim 17, wherein the edge contact electrically connects to a signal pad in a back-end-of-line (BEOL) region of the semiconductor die surrounded by a seal ring structure.
The IC structure of claim 12, wherein each edge pad of each semiconductor die includes a conductive line in a redistribution layer (RDL), the conductive line electrically connected to a signal pad in a back-end-of-line (BEOL) region of the semiconductor die surrounded by a seal ring structure.
The IC structure of claim 19, wherein the RDL includes a plurality of stacked dielectric layers within which the conductive line is located.

Description

FIELD This disclosure relates in general to a memory stack within IC structure, and more particularly to a high bandwidth memory stack with side edge interconnections and 3D IC structure including the same. BACKGROUND 2.5D/3D ICs have been recognized as a next generation semiconductor technology, which has the advantage of high performance, low power consumption, small physical size and high integration density. 2.5D/3D ICs provide a path to continue to meet the performance/cost demands of next generation devices while remaining at more relaxed gate lengths with less process complexity. Thus, 2.5D/3D ICs are expected to find broad based utilities in applications such as HPC (high-performance computing) and data centers, AI (artificial intelligence)/ML (machine learning), 5G/6G networks, graphics, smart phones/wearables, automotive and others that demand "extreme," ultra-high-performance, higher-power-efficiency devices. Commercial 2.5D/3D ICs such as a 3D high-bandwidth memory (HBM) DRAM memory die stack on logic are increasingly being used, and those HBM devices contain through silicon vias (TSVs) in both active dies and in the silicon interposer. Furthermore, 2.5D/3D ICs also allow for vertical stacking of heterogeneous dies from different manufacturing processes and nodes, chip reuse and chiplets-in-SiP (system-in-a-package) for high-performance applications, which have been already pushing the limits of a single die at the most advanced node. As shown in FIG. 1, a COWOS (chips-on-wafer-on-substrate) structure 20 includes an HBM structure 21 (with a plurality of DRAM memory dies 211 and a controller 213) with TSVs 201, a logic die 22 (such as a GPU or an SOC chip), a silicon interposer 23 with TSVs and a packaging substrate 24, wherein the HBM structure 21 and the logic die 22 are stacked on the silicon interposer 23, and the silicon interposer 23 is then stacked on the packaging substrate 24. However, 2.5D/3D ICs adopt packaging topologies with bottom/top electrical interconnects created by the aforementioned interconnect technologies such as micro-bumps, TSVs and redistribution layers (RDL). The bottom/top electrical interconnects impose a severe constraint on PPAC (power, performance, area and cost) optimization by designers of 3D ICs to come up with optimal design solutions, especially the difficulty of forming TSVs in semiconductor dies and the alignment of TSVs for each semiconductor die. Furthermore, as the monolithic integration capability of a silicon chip has grown from GSI (Giga Scale Integration: Over billions of transistors on a die) toward TSI (Tera Scale Integration: Trillions of transistors on a die) soon, the power consumption of running such a huge number of transistors is increasing sharply, which elevates adversely the junction temperature of transistors and thus the entire chip temperature due to current limited heat-dissipation capability (e.g. Thermal conductivity index of silicon dioxide/ silicon is very low. To be worse, due to the stack of multiple DRAM memory semiconductor dies (or HBM) in 2.5D/3D ICs, the insufficient heat dissipation problem causing higher temperature to chip operation is regarded as the worst problem for the HBM structure. SUMMARY According to a first aspect of the present disclosure, an IC structure includes a memory stack, wherein the memory stack includes a plurality of semiconductor dies horizontally separate with each other, wherein each semiconductor die has a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads arranged along the first sidewall. The area of the bottom surface or the top surface of each semiconductor die is larger than that of any sidewall. The IC structure further includes a logic die with memory controller and processor circuit under the memory stack and electrically connected to the plurality of edge pads of each semiconductor memory die, and a packaging substrate under and electrically connected to the logic die with memory controller and processor. There is no interposer between the packaging substrate and the logic die with memory controller and processor circuit, and there is no TSV in each semiconductor die. According to some embodiments of the present disclosure, the IC structure further includes an upward extending thermal conductivity layer and/or a laterally extending thermal conductivity layer. The upward extending thermal conductivity layer is disposed between two adjacent semiconductor dies. The thermal conductivity of the upward extending thermal conductivity layer is higher than that of Si or SiO2. The laterally extending thermal conductivity layer covers each second sidewall of the plurality of semiconductor dies and is thermally coupled to the upward extending thermal conductivity layer, wherein the laterally extending thermal conductivity layer is opposite to the first sidewalls of