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EP-4739076-A1 - WIRE-BOND STRUCTURE FOR POWER PACKAGES TO REDUCE RDSON

EP4739076A1EP 4739076 A1EP4739076 A1EP 4739076A1EP-4739076-A1

Abstract

A semiconductor device, a semiconductor package comprising such semiconductor device and a method of manufacturing such semiconductor package are presented. The semiconductor device comprises a die (202) and a leadframe (204). The semiconductor device further comprises a wire-bond interconnect structure comprising one or more pairs (208) of wires. Herein, a pair (208) of wires comprises two wires that are bonded together at one end at the die (202) and that are bonded together on the other end at the leadframe (204).

Inventors

  • Zhong, Chenchao
  • FLAUTA, RANDOLPH ESTAL
  • FAN, HAIBO

Assignees

  • Nexperia B.V.

Dates

Publication Date
20260506
Application Date
20251029

Claims (15)

  1. A semiconductor device comprising a die (202) and a leadframe (204), and further comprising: a wire-bond interconnect structure comprising one or more pairs (208) of wires, wherein a pair (208, 300) of wires comprises two wires (302, 304) that are bonded together at one end at the die (202) and that are bonded together on the other end at the leadframe (204).
  2. The semiconductor device according to claim 1, wherein the pair (300) of wires comprises a first wire (302) that is wedge bonded (306) to the die (202) at one end of the first wire (302) and that is wedge bonded (306) to the leadframe (204) at the other end of the first wire (302).
  3. The semiconductor device according to claim 2, wherein the pair (300) of wires further comprises a second wire (304) that is ball bonded (308) to the first wire (302) at the die (202) at one end of the second wire (304) and that is stitch bonded (310) to the first wire (302) at the leadframe (204) at the other end of the second wire (304).
  4. The semiconductor device according to claim 2, wherein the pair (208) of wires further comprises a second wire that is stitch bonded to the first wire at the die (202) at one end of the second wire and that is ball bonded to the first wire at the leadframe (204) at the other end of the second wire.
  5. The semiconductor device according to claim 2, wherein the pair (208) of wires further comprises a second wire that is wedge bonded to the first wire at the die (202) at one end of the second wire and that is wedge bonded to the first wire at the leadframe (204) at the other end of the second wire.
  6. The semiconductor device according to any one of the claims 1-5, wherein the two wires of the pair of wires have a same or similar thickness.
  7. The semiconductor device according to claim 6, wherein the two wires of the pair of wires have a same of similar thickness in a range of about 75µm to about 500µm, preferably about 75µm.
  8. The semiconductor device according to any one of the claims 1-5, wherein the two wires of the pair of wires have different thicknesses.
  9. The semiconductor device according to claim 8, wherein the first wire (302) has a thickness in a range of about 75µm to about 500µm, wherein the second wire (304) has a thickness in a range of about 75µm to about 500µm, and wherein the thickness of the first wire (302) is different from the thickness of the second wire (304).
  10. The semiconductor device according to claim 8, wherein the first wire (302) has a thickness in a range of about 75µm to about 500µm, wherein the second wire (304) has a thickness in a range of about 16µm to about 75µm, and wherein the thickness of the first wire (302) is different from the thickness of the second wire (304).
  11. The semiconductor device according to any one of the preceding claims, wherein the semiconductor device is a power semiconductor device, preferably a power Metal Oxide Silicon Field Effect Transistor, power-MOSFET.
  12. A semiconductor package comprising a semiconductor device according to any one of the claims 1-11.
  13. The semiconductor package according to claim 12, wherein the semiconductor package is a Micro Leadframe Package, MLPAK, preferably an MLPAK56 package.
  14. A method of manufacturing (400) a semiconductor package according to claim 12 or claim 13, the method comprising: providing (402) a die (202) and a leadframe (204); applying (404) a first wire (302) between the die (202) and the leadframe (204) by bonding the ends of the first wire (302) to the die (202) and the leadframe (204), respectively; applying (406) a second wire (304) between the die (202) and the leadframe (204) by bonding the ends of the second wire (304) to the ends of the first wire (302) at the die (202) and at the leadframe (204), respectively.
  15. The method according to claim 14, comprising: wedge bonding (306) the first wire (302) to the die (202) at one end of the first wire (302) and wedge bonding (306) the first wire (302) to the leadframe (204) at the other end of the first wire (302); and ball bonding (308) the second wire (304) to the first wire (302) at the die (202) at one end of the first wire (302) and stitch bonding (310) the second wire (304) to the first wire (302) at the leadframe (204) at the other end of the first wire (302), or stitch bonding the second wire to the first wire at the die (202) at one end of the first wire and ball bonding the second wire to the first wire at the leadframe (204) at the other end of the first wire, or wedge bonding the second wire to the first wire at the die (202) at one end of the first wire and wedge bonding the second wire to the first wire at the leadframe (204) at the other end of the first wire.

Description

Technical field The present disclosure relates to a semiconductor device, a semiconductor package comprising such semiconductor device. More specifically, the present disclosure relates to wire-bonding in such semiconductor device. Background Drain-to-Source On Resistance (Rdson), i.e., the resistance between the drain and source terminals when turned on, is a critical parameter in power packages, particularly in power Metal Oxide Silicon Field Effect Transistors (MOSFETs) and other power semiconductor devices. It plays a significant role in determining the performance, efficiency, and thermal behavior of these devices. For example, in relation to power dissipation and efficiency, Rdson can directly affect the amount of power the device dissipates during operation. A lower Rdson reduces power loss, making the device more efficient, especially in high-current applications. In power packages like those used in power converters, motor drives, and switching regulators, minimizing Rdson maximizes efficiency and minimize energy loss. In another example, in relation to thermal management, power devices generate heat due to power dissipation, and Rdson can be a major contributor to this. Lower Rdson results in lower power dissipation, which leads to reduced heat generation. This is important because excessive heat can degrade the performance, reliability, and lifespan of semiconductor devices. In power packages, optimizing Rdson helps minimize the need for additional cooling solutions like heatsinks or fans, reducing overall system cost and complexity. In another example, in relation to switching performance, in applications involving switching, such as Direct Current (DC) to DC converters or inverters, Rdson can influence the overall switching speed and performance. Although Rdson primarily affects conduction losses (when the device is on), it indirectly impacts switching behavior by influencing the thermal profile and efficiency. Efficient thermal management achieved through lower Rdson helps maintain consistent performance during fast switching cycles, reducing the risk of thermal runaway or device failure. In another example, in relation to size and compactness of power packages, a lower Rdson allows for smaller and more compact power packages. When devices generate less heat, they can be designed with smaller footprints without sacrificing performance. This can be crucial in modern applications where size, weight, and space are critical factors, such as in electric vehicles and portable electronics. In another example, in relation to impact on system reliability, since Rdson can directly affect power dissipation and heat generation, it can also impact the long-term reliability of the power package. Excessive heat due to high Rdson can lead to thermal cycling failures due to stresses on the device and its packaging materials. Over time, this can cause failures like bond wire fatigue or solder joint cracking. By minimizing Rdson, manufacturers can improve the durability and reliability of power devices, ensuring they can withstand harsh operating conditions and prolonged use. Summary A summary of aspects of certain examples disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these certain embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, this disclosure may encompass a variety of aspects and/or a combination of aspects that may not be set forth. The present disclosure presents an improved wire-bond structure for power semiconductor devices and power packages including such power semiconductor device to reduce Rdson. Furthermore, a method of manufacturing such improved wire-bond structure is presented. According to an aspect of the present disclosure, a semiconductor device is presented. The semiconductor device may include a die and a leadframe. The semiconductor device may further include a wire-bond interconnect structure. The wire-bond interconnect structure may include one or more pairs of wires. A pair of wires includes two wires that are bonded together at one end at the die and that are bonded together on the other end at the leadframe. In an embodiment, the pair of wires may include a first wire that is wedge bonded to the die at one end of the first wire and that is wedge bonded to the leadframe at the other end of the first wire. In an embodiment, the pair of wires may further include a second wire that is ball bonded to the first wire at the die at one end of the second wire and that is stitch bonded to the first wire at the leadframe at the other end of the second wire. In another embodiment, the pair of wires may further include a second wire that is stitch bonded to the first wire at the die at one end of the second wire and that is ball bonded to the first wire at the leadframe at the other end of the second wire. In another embodiment, the pair of wires m