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EP-4739077-A1 - A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND CORRESPONDING SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR PACKAGE

EP4739077A1EP 4739077 A1EP4739077 A1EP 4739077A1EP-4739077-A1

Abstract

In the first aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device (100), comprising the steps of: - providing a substrate (110); - mounting a semiconductor die (120) having a first die surface and a second die surface opposite to the first die surface, with its first die surface to the substrate; - mounting a spacer (140) having a first spacer surface and a second spacer surface opposite to the first spacer surface, with its first spacer surface on the second die surface; - fusing bonding means (150) to the second spacer surface by means of ultrasonic fusing.

Inventors

  • POELMA, Regnerus Hermannus
  • SHI, Ziliang
  • Högerl, Jürgen

Assignees

  • Nexperia B.V.

Dates

Publication Date
20260506
Application Date
20251029

Claims (14)

  1. A method of manufacturing a semiconductor device, comprising the steps of: - providing a substrate; - mounting a semiconductor die having a first die surface and a second die surface opposite to the first die surface, with its first die surface to the substrate; - mounting a spacer having a first spacer surface and a second spacer surface opposite to the first spacer surface, with its first spacer surface on the second die surface; - fusing bonding means to the second spacer surface by means of ultrasonic fusing.
  2. The method according to claim 1, wherein the mounting of the spacer to the semiconductor die is performed by diffusion soldering.
  3. The method according to any of the preceding claims, wherein the method comprises a further step before the step of mounting the spacer to the semiconductor die, wherein the further step comprises providing a connection layer onto the first spacer surface.
  4. The method according to claim 3, wherein providing a connection layer is performed by stamping the spacer with its first spacer surface onto a metal film.
  5. A semiconductor device comprising: a substrate; a semiconductor die having a first die surface and a second die surface opposite to the first die surface, wherein the first die surface is mounted on the substrate; a spacer having a first spacer surface and a second spacer surface opposite to the first spacer surface, with its first spacer surface mounted to the second die surface; bonding means directly fused to the second spacer surface.
  6. The semiconductor device according to claim 5, wherein a thickness of the spacer is at least 100 µm, more preferably at least 200 µm, most preferably at least 300 µm.
  7. The semiconductor device according to any of the claims 5-6, wherein a material of the spacer is a metallic material comprising any of copper, a copper alloy, molybdenum, aluminum, or molybdenum alloy.
  8. The semiconductor device according to any of the claims 5-7, wherein the first spacer surface is smaller than the second die surface.
  9. The semiconductor device according to any of the claims 5-8, wherein the spacer comprises a connection layer provided on its first spacer surface.
  10. The semiconductor device according to claim 9, wherein the connection layer is made of a lead-free metallic material selected from a list not limiting: Tin Bismuth (Sn-Bi), Tin-Silver (Sn-Ag), Tin-Gold (Sn-Au), Tin-Indium (Sn-In), Tin-Antimony (Sn-Sb), Tin-Palladium (Sn-Pd), and Tin-Zinc (Sn-Zn).
  11. The semiconductor device according to any of the claims 9-10, wherein a thickness of the connection layer is less than 100 µm, preferably less than 50 µm, more preferably less than 10 µm.
  12. The semiconductor device according to any of the claims 9-11, wherein the connection layer is only partially provided on the spacer, such that at least a part of the first spacer surface is exposed.
  13. The semiconductor device according to any of the claims 5-11, wherein the bonding means are a bond clip.
  14. A semiconductor package comprising the semiconductor device according to any of the preceding claims, wherein the semiconductor package further comprises: a source, a drain and a gate terminal, each operatively connected to the semiconductor device; an encapsulant at least substantially encapsulating the semiconductor package, wherein at least part of the source, drain and gate terminal are exposed to allow electrical connection to the semiconductor package.

Description

Technical Field The present disclosure relates to methods of manufacturing a semiconductor device and a corresponding semiconductor device as well as a semiconductor package. Background Clip-bonding is a technique that is used in the semiconductor industry to provide electrical connection to semiconductor dies. In this method, a metal clip is soldered onto the semiconductor die, providing a robust and efficient connection compared to wire-bonding. This approach improves the current-carrying capacity, as the metal clip offers a thicker and more reliable electrical path than the thin wires used in wire-bonding. Additionally, clip-bonding enhances thermal dissipation by utilizing the clip's larger surface area to transfer heat more effectively from the die to the heat sink, which is essential in high-power applications where managing heat is crucial for device reliability. To realize the connection between the metal clip and the semiconductor die, soldering is used to provide a mechanical and electrical bond between the clip and the die. During the process, both the metal clip and the die are heated to the solder's melting point, allowing the solder to flow and create a durable bond upon cooling. Solder materials that are typically used comprise lead. Lead-based solders often have a high melting point, because of their fatigue resistance and long-term reliability. Furthermore, lead provides good wetting, this may ensure a strong and uniform bond. Other advantages include the ductility of the element and the high electrical conductivity. However, lead is in recent times regarded more and more as an unwanted element due to its toxicity to human health. Products containing lead may end up in unwanted contact with humans which may be detrimental to their overall well-being and health. Furthermore, it can contaminate soil and water it contacts. Summary It is thus the goal of the disclosure to achieve a semiconductor device which omits the use of lead. As the use of lead regarding the soldering process, it would be advantageous to provide a method of manufacturing such a semiconductor device without using lead. In the first aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, comprising the steps of: providing a substrate;mounting a semiconductor die having a first die surface and a second die surface opposite to the first die surface, with its first die surface to the substrate;mounting a spacer having a first spacer surface and a second spacer surface opposite to the first spacer surface, with its first spacer surface on the second die surface;fusing bonding means to the second spacer surface by means of ultrasonic fusing. It has been found that bonding means, such as bond clips, can be effectively connected to a spacer on a semiconductor die using ultrasonic, US, soldering or US welding, preferably US welding. This is a fusing process in which highfrequency ultrasonic vibrations are applied to two parts of the device under pressure and sometimes at elevated temperatures. The ultrasonic vibrations cause localized friction and heat at the interface of the materials. This frictional heat is sufficient to soften or melt the materials, leading to a solid-state bond, also known as fusion, without the need for external heating or melting of the entire material. This way the interface between the spacer and the bonding means are no longer present and no barrier longer exists for the current to pass. Furthermore, with this method a strong and electrically conductive connection can be made without the need of using any solder and is therefore the ultimate lead-free method. One drawback of US soldering or US welding is that the vibrations can be detrimental for the semiconductor die. They could lead to breakage or chipping, making the semiconductor unusable. It has been found that including a spacer in this process results in a dampening of the vibrations on the semiconductor die. This principle is known as the Saint Vernant's principle, wherein localized high stress is redistributed in the surrounding material. Thus when a spacer is used the concentrated stress from the fusing process on one side results in a redistributed and thus diminishes stress on the other side, such that that material on one side can be fused, while the other is not harmed. Not only vibrations are to be shielded, but the spacer also provides a shield for the heat resulting from the US soldering or US welding process. By employing the spacer, the heat is dissipated throughout the spacer, ensuring no harmful effects result at the semiconductor from the US soldering or US welding process. An additional benefit that is achieved by mounting a spacer onto the semiconductor die prior to fusing the bonding means there onto, is that a simpler design may be employed for the bonding means and that the constraints for a positioning device for positioning the bonding means can be relaxed. Namely, positioning a rel