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EP-4739080-A1 - A METHOD OF MANUFACTURING A PLURALITY OF SEMICONDUCTOR DEVICES AS WELL AS A CORRESPONDING SEMICONDUCTOR DEVICE

EP4739080A1EP 4739080 A1EP4739080 A1EP 4739080A1EP-4739080-A1

Abstract

A method of manufacturing a plurality of semiconductor devices, wherein the method comprises the steps of providing a carrier layer comprising a first surface and a second surface opposite to the first surface, attaching a first metallization layer to the first surface of the carrier layer, transferring a metal paste to the first metallization layer for creating first patterned metal pads and dicing the carrier layer to provide the plurality of semiconductor devices.

Inventors

  • POELMA, Regnerus Hermannus
  • BROWN, ADAM
  • Khaderbad, Mrunal
  • Syré, Jörg

Assignees

  • Nexperia B.V.

Dates

Publication Date
20260506
Application Date
20251031

Claims (15)

  1. A method of manufacturing a plurality of semiconductor devices, wherein the method comprises the steps of: - providing a carrier layer comprising a first surface and a second surface opposite to the first surface; - attaching a first metallization layer to the first surface of the carrier layer; - transferring a metal paste to the first metallization layer for creating first patterned metal pads, - dicing the carrier layer to provide the plurality of semiconductor devices.
  2. A method in accordance with claim 1, wherein said method further comprises the step of: - creating a connection between the metal pads and a clip and or leadframe to form a clip-bonded product.
  3. A method in accordance with any of the previous claims, wherein said method further comprises the step of: - sintering said transferred metal paste to form a solidified metal layer.
  4. A method in accordance with claim 3, wherein a porosity of the solidified metal layer is in a range of 1% to 30% and, preferably, between 5% - 10%.
  5. A method in accordance with any of the previous claims and at least to claim 2, wherein said step of creating comprises: - applying a solder paste or solder material or sinter paste to create the connection to said clip or said leadframe.
  6. A method of manufacturing according to any of the previous claims, wherein the method comprises the additional steps of: - attaching a second metallization layer to the second surface of the carrier layer prior to the step of dicing; - transferring a metal paste to the to the second metallization layers, prior to the step of dicing, for creating second patterned metal pads.
  7. A method of manufacturing in accordance with any of the previous claims, wherein a thickness of the first patterned metal pads exceeds alpha particle penetration depth, wherein the alpha particle penetration depth denotes a depth at which alpha particles are at least substantially absorbed by the metal pad.
  8. A method of manufacturing in accordance with any of the previous claims, wherein a thickness of the first patterned metal pads provide current redistribution and mechanical protection to said semiconductor dies as well as making corresponding surfaces suitable for soldering.
  9. A method of manufacturing in accordance with any of the previous claims, wherein the first and/or second patterned metal pads comprises a thickness of 1-50 um, preferably 5-35 um and even more preferably 20-30 um.
  10. A method of manufacturing in accordance with any of the previous claims, wherein the metal paste is any of a copper-based paste, a silver-based paste, tin-based, gold-based, aluminium-based or an alloy of one or more of these metals.
  11. A method of manufacturing in accordance with claim 10, wherein the metal paste further comprises polymers and/or fillers.
  12. A method of manufacturing in accordance with any of the previous claims, wherein the step of transferring comprises any of screen printing or stencil printing or jetting or lifting the metal paste to the respective metallization layer.
  13. A semiconductor device manufactured by a method in accordance with any of the previous claims.
  14. A semiconductor device in accordance with claim 13, wherein said created first patterned metal pads is a solidified metal layer, wherein a porosity of the solidified metal layer is in a range of 1% to 30% and, preferably, between 5% - 10%.
  15. A semiconductor device in accordance with any of the claims 13 - 14, wherein said semiconductor device is any of a Metal Oxide Semiconductor, MOS, Field Effect Transistor, FET, a Bipolar Junction Transistor, BJT, a Diode.

Description

Technical field The present disclosure relates to the field of manufacturing semiconductor devices and, more specifically, to an efficient way of manufacturing semiconductor devices. Background In the field of power semiconductors, device resistance is an important factor that may influence both performance and efficiency. The total device resistance can be broken down into three main components: Resistance of the semiconductor switch. This is typically located in the top 2-10 micrometres of the silicon, Si, wafer.Resistance of the silicon substrate. This typically refers to the resistance of the doped silicon, which initially measures around 500-800 micrometres in thickness.Resistance of the package interconnects. These are the connections that link the semiconductor die to external circuits. Lowering the overall resistance leads to better device performance and higher efficiency in the final product. Various strategies have been employed to minimize resistance in each of these areas, with notable advancements in recent years. One method for reducing package resistance has been the replacement of traditional wire bond interconnects with soldered clip contacts. While this technique has proven effective, it comes with a downside: the solder used often contains lead, Pb, which includes radioactive isotopes. Over time, these isotopes emit alpha radiation that can damage the semiconductor structure or cause shifts in its electrical behaviour. Another approach focuses on reducing the thickness of the silicon substrate. Typically, substrates are thinned through grinding and chemical stress relief to approximately 100 micrometres. However, in recent years, there has been a push toward thinning substrates even further, to 50 micrometres or below, in order to reduce resistance and enhance heat dissipation. Unfortunately, the trade-off is that such thin wafers, particularly those with diameters of 200 mm or 300 mm, become highly fragile. This increased fragility can negatively impact mechanical yield during the manufacturing process. In terms of improving the resistance of the current spreading layer, one solution has been to increase the thickness of the metallization on the top of the die. Historically, this layer has been less than 1 micrometre thick, but increasing it to 4 micrometres has been shown to reduce resistance and improve the overall performance of the device. To address many of these issues, plating thick copper layers on the wafer's front side and/or backside has emerged as a solution. Copper layers between 10 and 20 micrometres thick offer several advantages. First, a copper layer of at least 11.8 micrometres is sufficient to block alpha radiation at particle energy levels of 5.5 MeV, providing significant protection for the semiconductor. This not only shields the semiconductor from radiation damage but also improves the long-term reliability of the device. Moreover, thick copper metallization enhances the device's ability to handle high surge currents by reducing hotspots and spreading resistance. The copper layers can also bolster the mechanical strength of the wafer and individual dies, thereby improving both wafer yield and assembly yield during manufacturing. Additionally, copper layers can be soldered to, facilitating easier assembly to copper clips and offering a practical drop-in solution for clip bond assembly processes. However, these benefits come with certain disadvantages. Wafer-level pad metallization, particularly when it involves thick layers (greater than 1 micrometre), is both costly and time-consuming. Achieving thick metallization on the front or back of a wafer often requires sophisticated processes such as physical vapor deposition, PVD, and galvanic electroplating. These techniques are typically combined with lithography, etching, and lift-off steps to create the desired patterned layers. A significant drawback of these thick metallization layers is their potential to complicate the wafer singulation process, where the wafer is diced into individual dies. If not carefully managed, thick backside metallization can negatively affect the quality of this dicing process. While techniques such as copper layer plating offer significant improvements in resistance, mechanical robustness, and surge current performance, they also introduce complexities in the manufacturing process that must be carefully addressed to ensure high-quality, efficient power semiconductor devices. Summary It would be advantageous to achieve a method of manufacturing semiconductor devices, wherein the method is more efficient compared to prior art solutions. It would further be advantageous to achieve corresponding semiconductor devices. In a first aspect of the present disclosure, there is provided a method of manufacturing a plurality of semiconductor devices, wherein the method comprises the steps of: providing a carrier layer comprising a first surface and a second surface opposite to the first surface;atta