EP-4739082-A2 - WAFER-LEVEL CHIP-SCALE SEMICONDUCTOR DEVICE AND METHOD THEREFOR

EP4739082A2EP 4739082 A2EP4739082 A2EP 4739082A2EP-4739082-A2

Abstract

A method of forming a semiconductor device is provided. The method includes applying a first non-conductive layer onto an active side of a semiconductor wafer having a plurality of semiconductor die surrounded by singulation lanes. A trench is formed in the singulation lanes surrounding the semiconductor die and filled with a non-conductive filler. A backside of the semiconductor wafer is ground to expose the non-conductive filler through the backside of the semiconductor wafer. A second non-conductive layer is applied onto the backside of the semiconductor wafer. A singulation cut is formed through a portion of the non-conductive filler to form a plurality of individual packaged semiconductor device units. A predetermined portion of the non-conductive filler remains on each sidewall of the plurality of semiconductor die.

Inventors

Tien, Yujen
HUANG, WEN HUNG
Mao, Kuan-Hsiang
LIU, Yufu

Assignees

NXP B.V.

Dates

Publication Date: 20260506
Application Date: 20251027

Claims (15)

A method comprising: applying a first non-conductive layer onto an active side of a semiconductor wafer, the semiconductor wafer including a plurality of semiconductor die surrounded by singulation lanes; forming a trench in the singulation lanes surrounding the semiconductor die; filling the trench with a non-conductive filler; grinding a backside of the semiconductor wafer to expose the non-conductive filler through the backside of the semiconductor wafer; applying a second non-conductive layer onto the backside of the semiconductor wafer; and forming a singulation cut through a portion of the non-conductive filler to form a plurality of individual packaged semiconductor device units, a predetermined portion of the non-conductive filler remaining on each sidewall of the plurality of semiconductor die.
The method of claim 1, further comprising forming openings through the first non-conductive layer to expose top surface portions of bond pads of the semiconductor die.
The method of claim 2, further comprising forming a redistribution layer (RDL) structure over the first non-conductive layer, the RDL structure interconnected to the exposed top surface portions of bond pads of the semiconductor die.
The method according to any preceding claim, wherein forming the trench includes sawing, by way of a mechanical blade, from the active side of the wafer and to a predetermined depth.
The method according to any preceding claim, wherein filling the trench with the non-conductive filler includes filling the trench with a glass material by way of a jet dispensing process.
The method according to any preceding claim , wherein a width dimension of the singulation cut is less than a width dimension of the trench.
The method of claim 6, wherein a thickness of the predetermined portion of the non-conductive filler remaining on each sidewall of the plurality of semiconductor die is in a range of 10-30% of the width dimension of the trench.
The method according to any preceding claim, wherein the first non-conductive layer and the second non-conductive layer together with the predetermined portion of the non-conductive filler remaining on semiconductor die sidewalls are configured and arranged to provide six-sided protection for each of the individual packaged semiconductor device units.
The method according to any preceding claim, wherein the first non-conductive layer is formed from a material different from that of the second non-conductive layer.
A semiconductor device comprising: a semiconductor die having a plurality of bond pads; a first non-conductive layer applied on an active side of the semiconductor die; openings formed through the first non-conductive layer, the openings configured to expose top surface portions of the bond pads; a second non-conductive layer applied on backside of the semiconductor die; and a non-conductive sidewall material formed on each sidewall of the semiconductor die.
The semiconductor device of claim 10, wherein the first non-conductive layer and the second non-conductive layer together with the non-conductive sidewall material are configured and arranged to provide six-sided protection for the semiconductor device.
The semiconductor device of claim 10 or claim 11, further comprising a redistribution layer (RDL) structure formed over the first non-conductive layer, the RDL structure interconnected to the exposed top surface portions of bond pads of the semiconductor die.
The semiconductor device according to any of claim 10 to claim 12, wherein a portion of the non-conductive sidewall material overlaps a sidewall portion of the first non-conductive layer.
The semiconductor device according to any of claim 10 to claim 13, wherein the non-conductive sidewall material is characterized as a glass material.
The semiconductor device according to any of claim 10 to claim 14, wherein the first non-conductive layer is characterized as a dry film.

Description

Background Field This disclosure relates generally to semiconductor device packaging, and more specifically, to a wafer-level chip-scale semiconductor device and method of forming the same. Related Art Today, there is an increasing trend to include sophisticated semiconductor devices in products and systems that are used every day. These sophisticated semiconductor devices may include features for specific applications which may impact the configuration of the semiconductor device packages, for example. For some features and applications, the configuration of the semiconductor device packages may be susceptible to lower reliability, lower performance, and higher product or system costs. Accordingly, significant challenges exist in accommodating these features and applications while minimizing the impact on semiconductor devices' reliability, performance, and costs. Brief Description of the Drawings The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. FIG. 1 illustrates, in a simplified dimensional view, an example wafer-level chip-scale semiconductor device at a stage of manufacture in accordance with an embodiment.FIG. 2 through FIG. 7 illustrate, in simplified cross-sectional views, the example semiconductor device at stages of manufacture in accordance with an embodiment.FIG. 8 illustrates, in a simplified dimensional view, the example semiconductor device at a subsequent stage of manufacture in accordance with an embodiment.FIG. 9 through FIG. 11 illustrate, in simplified cross-sectional views, the example semiconductor device at subsequent stages of manufacture in accordance with an embodiment. Detailed Description Generally, there is provided, a wafer-level chip-scale semiconductor device having six-sided die protection. A first non-conductive layer is bonded on an active side of a semiconductor wafer containing a plurality of die surrounded by singulation lanes. A redistribution structure is formed over the first non-conductive layer and interconnected with bond pads of the die through openings formed in the first non-conductive layer. A continuous trench is formed along the singulation lanes such that each die is surrounded by the trench. The trench is subsequently filled with a filler material such as an epoxy compound or glass material. After the trench is filled, the backside of the semiconductor wafer is subjected to a grind operation to reduce the wafer thickness and expose the filler material through the backside of the wafer. A second non-conductive layer is bonded on the ground backside of the semiconductor wafer and exposed filler surface. A sandwich-like structure is formed with the semiconductor wafer sandwiched between the first non-conductive layer and the second non-conductive layer. After the second non-conductive layer is bonded on the backside of the semiconductor wafer, the sandwich-like structure is singulated to form a plurality of individual semiconductor device units. The singulation cut is formed having a width narrower than the width of the trench such that a filler coating portion remains on the sidewalls of each die after singulation. By forming the semiconductor device in this manner, a substantially thin, low-cost semiconductor device having six-sided die protection may be realized. FIG. 1 illustrates, in simplified dimensional view, an example wafer-level chip-scale semiconductor device 100 at a stage of manufacture in accordance with an embodiment. At this stage, a first non-conductive layer 108 is positioned over a semiconductor wafer 102. The non-conductive layer 108 may be provided as a preformed dry dielectric film such as Ajinomoto Build-up Film (ABF), for example. In this embodiment, the semiconductor wafer 102 is arranged in an active-side-up orientation and configured for the non-conductive layer 108 to be bonded at the active side during a subsequent stage of manufacture. The term "conductive," as used herein, generally refers to electrical conductivity unless otherwise described. Simplified cross-sectional views of the example semiconductor device 100 taken along line A-A at stages of manufacture are depicted in FIG. 2 through FIG. 7 and FIG. 9 through FIG. 11. The semiconductor wafer 102 includes a plurality of (pre-singulated) semiconductor die 104 surrounded by singulation lanes 106. The semiconductor wafer 102 has the active side (e.g., major side having circuitry) and a backside (e.g., major side opposite of the active side). The semiconductor die 104 includes bond pads (not shown) formed at the active side, for example. The semiconductor wafer 102 may be formed from any suitable semiconductor material, such as silicon, germanium, gallium arsenide, gallium nitride, and the like. The semiconductor die 104 of the semiconductor wafer 102 may inclu