Search

EP-4739083-A2 - SEMICONDUCTOR PACKAGE ASSEMBLY AND MANUFACTURING METHOD

EP4739083A2EP 4739083 A2EP4739083 A2EP 4739083A2EP-4739083-A2

Abstract

Disclosed in the embodiments of the disclosure are a semiconductor package assembly and a manufacturing method. The semiconductor package assembly includes: a base plate, having a first surface; a chip stacking structure, located on the base plate, where the chip stacking structure includes a plurality of chips sequently stacked in a direction perpendicular to the base plate, and is electrically connected to the first surface of the base plate; an interposer, located on the chip stacking structure and having a first interconnection surface, where the first interconnection surface has a first interconnection region and a second interconnection region, and the first interconnection region is electrically connected to the base plate; and a molding compound, sealing the chip stacking structure, the interposer and the first surface of the base plate. The first interconnection region is not sealed by the molding compound, and the second interconnection region is sealed by the molding compound. There is a preset height between a top surface of the molding compound on the second interconnection region and the first interconnection region.

Inventors

  • SUN, XIAOFEI
  • QUAN, Changhao

Assignees

  • Changxin Memory Technologies, Inc.

Dates

Publication Date
20260506
Application Date
20220808

Claims (15)

  1. A method for manufacturing a semiconductor package assembly, comprising: providing (501) a base plate (10), wherein the base plate (10) has a first surface (101); forming (502) a chip stacking structure (20) on the base plate (10), the chip stacking structure electrically connected to the first surface (101) of the base plate (10); forming (503) an interposer (30) on the chip stacking structure (20), wherein the interposer (30) has a first interconnection surface (301), the first interconnection surface (301) has a first interconnection region (31) and a second interconnection region (32), and the first interconnection region (31) is electrically connected to the base plate (10), in a direction perpendicular to the base plate (10), the base plate (10) has a first thickness, and the interposer (30) has a second thickness; and the first thickness is greater than the second thickness; a covering layer (80) with a preset height in the direction perpendicular to the base plate (10) is formed on the first interconnection region (31) of the interposer (30); using a first packaging mold (91) as a mask, to form a molding compound pre-layer (400) sealing the chip stacking structure (20), the interposer (30), the covering layer (80) and the first surface (101) of the base plate (10); the covering layer (80) is exposed by removing part of the molding compound pre-layer (400), whereby the remaining molding compound pre-layer (400) forming the molding compound (40); and the covering layer (80) is removed to expose the first interconnection region (31), the second interconnection region (32) is sealed by the molding compound (40), a preset height between a top surface (401) of the molding compound (40) on the second interconnection region (32) and the first interconnection region (31).
  2. The method of claim 1, wherein a surface of the first packaging mold (91) is parallel to a surface of the base plate (10), the first packaging mold (91) is located above the covering layer (80) and has a certain distance from the covering layer (80).
  3. The method of claim 2, further comprising: forming a second packaging mold (92), the second packaging mold (92) is located under a second surface (102) of the first base plate (10), and is parallel to the second surface (102), the first surface (101) and the second surface (102) are opposite to each other, wherein the first packaging mold (91) and the second packaging mold (92) are used as masks, to form the molding compound pre-layer (400), after the molding compound pre-layer (400) is formed, the first packaging mold (91) and the second packaging mold (92) are removed.
  4. The method of claim 3, wherein after removing the first packaging mold (91) and second packaging mold (92), the method further comprising: removing the molding compound pre-layer (400) under the base plate (10), to expose the second surface (102) of the base plate (10).
  5. The method of claim 4, wherein after the molding compound pre-layer (400) under the base plate (10) is removed to expose the second surface (102) of the base plate (10), part of the molding compound pre-layer (400) on the interposer (30) is removed to expose the covering layer (80).
  6. The method of claim 5, wherein after the molding compound (40) is formed, a base plate connection bump (17) is formed on the second surface (102) of the base plate (10).
  7. The method of claim 1, wherein a material of the covering layer (80) is polyimide, a polyester material, or a polyethylene terephthalate film; wherein a step of removing the covering layer (80) comprises: using a chemical solution to remove the covering layer (80), the used chemical solution dissolves the covering layer (80) without causing loss to the molding compound (40).
  8. The method of claim 1, wherein the chip stacking structure (20) comprises a plurality of chips (21) sequently stacked in a direction perpendicular to the base plate (10), each chip (21) has a first connection end (201), the method further comprising: after forming the interposer (30), a first conductive wire (51) is formed, each chip (21) is electrically connected to the base plate (10) via the first conductive wire (51); and a second conductive wire (52) is formed, the second interconnection region (32) is electrically connected to the base plate (10) via the second conductive wire (52).
  9. The method of claim 1, wherein the method further comprising: forming a second package structure (70), and forming a first solder ball (71) on the second package structure (70), the first solder ball (71) is electrically connected to the first interconnection region (31), a height of the first solder ball (71) is greater than the preset height between the top surface (401) of the molding compound (40) on the second interconnection region (32) and the first interconnection region (31).
  10. A method for manufacturing a semiconductor package assembly, comprising: providing (501) a base plate (10), wherein the base plate (10) has a first surface (101); forming (502) a chip stacking structure (20) on the base plate (10), the chip stacking structure electrically connected to the first surface (101) of the base plate (10); forming (503) an interposer (30) on the chip stacking structure (20), wherein the interposer (30) has a first interconnection surface (301), the first interconnection surface (301) has a first interconnection region (31) and a second interconnection region (32), and the first interconnection region (31) is electrically connected to the base plate (10); a covering layer (80) with a preset height in the direction perpendicular to the base plate (10) is formed on the first interconnection region (31) of the interposer (30); using a first packaging mold (91) as a mask, to form a molding compound pre-layer (400) sealing the chip stacking structure (20), the interposer (30), the covering layer (80) and the first surface (101) of the base plate (10); the covering layer (80) is exposed by removing part of the molding compound pre-layer (400), whereby the remaining molding compound pre-layer (400) forming the molding compound (40); and the covering layer (80) is removed to expose the first interconnection region (31), the second interconnection region (32) is sealed by the molding compound (40), a preset height between a top surface (401) of the molding compound (40) on the second interconnection region (32) and the first interconnection region (31).
  11. A semiconductor package assembly, comprising: a base plate (10), having a first surface (101); a chip stacking structure (20), located on the base plate (10), electrically connected to the first surface (101) of the base plate (10); an interposer (30), located on the chip stacking structure (20) and having a first interconnection surface (301), wherein the first interconnection surface (301) has a first interconnection region (31) and a second interconnection region (32), and the firstinterconnection region (31) is electrically connected to the base plate (10); and a molding compound (40), sealing the chip stacking structure (20), the interposer (30) and the first surface (101) of the base plate (10), wherein the first interconnection region (31) is not sealed by the molding compound (40), the second interconnection region (32) is sealed by the molding compound (40), and there is a preset height between a top surface of the molding compound (40) on the second interconnection region (32) and the first interconnection region (31); wherein, in a direction perpendicular to the base plate (10), the base plate (10) has a first thickness, and the interposer (30) has a second thickness; and the first thickness is greater than the second thickness.
  12. The semiconductor package assembly of claim 11, wherein the base plate (10) further comprising a first signal transmission region (110) and a second signal transmission region (120) that are respectively located on two opposite sides of the base plate (10), the first signal transmission region (110) is electrically connected to the chip stacking structure (20), the second signal transmission region (120) is electrically connected to the interposer (30), the first signal transmission region (110) and the second signal transmission region (120) are not connected to each other.
  13. The semiconductor package assembly of claim 11, further comprising: a first conductive wire (51) that electrically connects each chip (21) to the base plate (10); a second conductive wire (52), the second interconnection region (32) is electrically connected to the base plate (10) via the second conductive wire (52), the first conductive wire (51) and the second conductive wire (52) that are respectively located on two opposite sides of the chip stacking structure (20); each chip (21) has a first connection end (201), the first connection end (201) and the first signal transmission region (110) are located on the same side, the first conductive wire (51) is led out from the first connection end (201) to the first signal transmission region (110); and a plurality of first pads (311) are formed on the first interconnection region (31), a second pad (321) is formed on the second interconnection region (32), a second conductive wire (52) is led out from the second pad (321) to the second signal transmission region (120), wherein a number of the second pads (321) is greater than a number of the first pads (311); and an area of each of the second pads (321) is less than an area of each of the first pads (311).
  14. The semiconductor package assembly of claim 11, wherein an included angle between a sidewall between the top surface of the molding compound (40) and the first interconnection region (31) and a direction perpendicular to the base plate (10) is a first included angle; and the first included angle is greater than or equal to 0° and less than 90°.
  15. The semiconductor package assembly of claim 11, further comprising: a second package structure (70), comprising a first solder ball (71), wherein the first solder ball (71) is electrically connected to the first interconnection region (31), and there is a preset height between a top surface of the molding compound (40) on the second interconnection region (32) and the first interconnection region (31), a height of the first solder ball (71) is greater than the preset height.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application is a divisional of, and claims priority to EPO patent application No. 22786873.4, entitled "SEMICONDUCTOR PACKAGE ASSEMBLY AND MANUFACTURING METHOD", filed on August 8, 2022, which is based upon and claims priority to Chinese Patent Application No. 202210806367.7, filed on July 8, 2022, and entitled "SEMICONDUCTOR PACKAGE ASSEMBLY AND MANUFACTURING METHOD", the disclosure of which is hereby incorporated by reference in its entirety. TECHNICAL FIELD The disclosure relates to the technical field of semiconductors, and in particular, to a semiconductor package assembly and a manufacturing method. BACKGROUND All sectors, industries and regions continually require lighter, faster, smaller, more functional, more reliable and more cost-effective products in the electronics industry. In order to meet these growing requirements of many different consumers, more circuits are required to be integrated to provide required functions. In almost all applications, there is a growing requirement for reduced sizes, enhanced performance and improved functions of the integrated circuits. SUMMARY In view of this, embodiments of the disclosure provide a semiconductor package assembly and a manufacturing method. The invention is set out in the appended set of claims. In the embodiments of the disclosure, through the arrangement of the interposer, the subsequent second package structure may be connected to the chip stacking structure and the base plate via the first interconnection region on the interposer. Therefore, the interconnection among the chip structures of different types or different specifications can be realized, so as to cause a combination among different chip structures to be more flexible. In addition, since the chip stacking structure and the second package structure subsequently connected to the chip stacking structure are packaged independently, test and failure analysis are easier to perform. Since there is the preset height between the first interconnection region of the interposer and the top surface of the molding compound, the second package structure may be placed on the first interconnection region, within a region enclosed by the molding compound, so that the height and size of the entire structure can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS In order to more clearly illustrate the technical solutions in the embodiments of the disclosure or conventional technologies, the drawings used in the embodiments will be briefly described below. It is apparent that the drawings in the following descriptions are merely some embodiments of the disclosure. Other drawings can be conceived from those skilled in the art according to these drawings without any creative work. FIG. 1 is a schematic structural diagram of a semiconductor package assembly.FIG. 2 is a schematic structural diagram of a base plate.FIG. 3 is a schematic structural diagram of an interposer.FIG. 4 is a schematic structural diagram of a semiconductor package assembly.FIG. 5 is a schematic flowchart of a method for manufacturing a semiconductor package assembly.FIG. 6A to FIG. 6I are schematic diagrams of a device structure of a semiconductor package assembly during manufacturing. In the drawings: 1-Circular ring; 2-Carrier band;10-Base plate; 101-First surface; 102-Second surface; 11-Base plate substrate; 12-Base plate upper insulating dielectric layer; 13-Base plate lower insulating dielectric layer; 14-Base plate upper connection pad; 15-Base plate lower connection pad; 16-Base plate connection via; 17-Base plate connection bump; 110-First signal transmission region; 120-Second signal transmission region; 130-Third signal transmission region;20-Chip stacking structure; 21-Chip; 201-First connection end;30-Interposer; 31-First interconnection region; 32-Second interconnection region; 301-First interconnection surface; 311-First pad; 321-Second pad; 33-Base; 34-Intermediary upper insulating dielectric layer; 35-Intermediary lower insulating dielectric layer;40-Molding compound; 401-Top surface; 400-Molding compound pre-layer;51-First conductive wire; 52-Second conductive wire;60-Adhesive film;70-Second package structure; 71-First solder ball; 72-Second base plate; 73-Second molding compound;80-Covering layer;91-First packaging mold; 92-Second packaging mold. DETAILED DESCRIPTION Exemplary embodiments disclosed in the disclosure are described in more detail with reference to drawings. Although the exemplary embodiments of the disclosure are shown in the drawings, it is to be understood that the disclosure may be implemented in various forms and should not be limited by the specific embodiments described here. On the contrary, these embodiments are provided for more thorough understanding of the disclosure, and to fully convey a scope disclosed in the embodiments of the disclosure to a person skilled in the art. In the following descriptions, a lot of specific details are given in or