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EP-4739085-A2 - SYSTEMS AND METHODS OF THERMAL DISSIPATION VIAS FOR STACKED MEMORY MODULES

EP4739085A2EP 4739085 A2EP4739085 A2EP 4739085A2EP-4739085-A2

Abstract

Provided are systems, methods, and apparatuses for thermal dissipation vias for stacked memory modules (e.g., HBM modules). In one or more examples, the systems, devices, and methods include routing, for heat dissipation, a first through-silicon via, TSV, (555-a) vertically between a first stack of memory (515-a) and a second stack of memory (515-b); routing, for heat dissipation, a second TSV (555-b) horizontally between at least one of: a physical layer, PHY, of the first stack of memory (515-a) and a first memory die of the first stack of memory (515-a), or a PHY of the second stack of memory (515-b) and a first memory die of the second stack of memory (515-b).

Inventors

  • JEONG, HYOUN KWON

Assignees

  • Samsung Electronics Co., Ltd.

Dates

Publication Date
20260506
Application Date
20251022

Claims (14)

  1. A stacked integrated circuit, IC, device (500) comprising: a first through-silicon via, TSV, (555-a) for heat dissipation routed vertically adjacent to at least one of a first stack of dies (515-a) or a second stack of dies (515-b); and a second TSV (555-b) for heat dissipation routed horizontally between at least one of: a physical layer, PHY, (530-a) of the first stack of dies (515-a) and a first IC die of the first stack of dies (515-a), or a PHY of the second stack of dies (515-b) and a first IC die of the second stack of dies (515-b).
  2. The stacked IC device (500) of claim 1, wherein the first TSV (555-a) connects to a first metal layer (510) positioned above the first stack of dies (515-a) and the second stack of dies (515-b).
  3. The stacked IC device (500) of claim 2, wherein a heat sink (505) is positioned on a top surface of the first metal layer.
  4. The stacked IC device (500) of any one of claims 1 to 3, wherein the first TSV (555-a) connects to a second metal layer (560) below the first stack of dies (515-a) and the second stack of dies (515-b).
  5. The stacked IC device (500) of claim 4, wherein the second metal layer (560) is below at least one of the PHY of the first stack of dies (515-a) or the PHY of the second stack of dies (515-b).
  6. The stacked IC device (500) of any one of claims 1 to 5, wherein the second TSV (555-b) connects to at least one of a first metal sidewall adjacent to an outer surface of the first stack of dies (515-a) or a second metal sidewall adjacent to an outer surface of the second stack of dies (515-b).
  7. The stacked IC device (500) of any one of claims 1 to 6, wherein at least one of the first TSV (555-a) or the second TSV (555-b) is routed through a semiconductor that is deposited over at least one of the first stack of dies or the second stack of dies.
  8. The stacked IC device (500) of any one of claims 1 to 7, wherein the second TSV (555-b) connects to the first TSV (555-a).
  9. The stacked IC device (500) of any one of claims 1 to 8, further comprising a third TSV routed horizontally between at least one of: the first IC die of the first stack of dies (515-a) and a second IC die of the first stack of dies (515-a), or the first IC die of the second stack of dies (515-b) and a second IC die of the second stack of dies (515-b).
  10. The stacked IC device (500) of any one of claims 1 to 8, wherein: the first stack of dies (515-a) is a first stack of memory, the second stack of dies (515-b) is a second stack of memory, the first IC die of the first stack of dies (515-a) is a first memory die of the first stack of memory, and the first IC die of the second stack of dies (515-b) is a first memory die of the second stack of memory.
  11. The stacked IC device (500) of claim 10, further comprising a third TSV routed horizontally between at least one of: the first memory die of the first stack of memory and a second memory die of the first stack of memory, or the first memory die of the second stack of memory and a second memory die of the second stack of memory.
  12. A method of thermal dissipation, the method comprising: routing (605, 705), for heat dissipation, a first through-silicon via, TSV, (555-a) vertically adjacent to at least one of a first stack of memory (515-a) or a second stack of memory (515-b); and routing (610, 710), for heat dissipation, a second TSV (555-b) horizontally between at least one of: a physical layer (PHY) of the first stack of memory (515-a) and a first memory die of the first stack of memory (515-a), or a PHY of the second stack of memory (515-b) and a first memory die of the second stack of memory (515-b).
  13. The method of claim 12, further comprising routing (715) a third TSV horizontally between at least one of: the first memory die of the first stack of memory (515-a) and a second memory die of the first stack of memory (515-a), or the first memory die of the second stack of memory (515-b) and a second memory die of the second stack of memory (515-b).
  14. The method of claim 12 or 13, wherein the first TSV (555-a) connects to a first metal layer (510) positioned above each of the first stack of memory (515-a) and the second stack of memory (515-b).

Description

TECHNICAL FIELD The disclosure relates generally to memory systems, and more particularly to thermal dissipation vias for stacked memory modules. BACKGROUND The present background section is intended to provide context only, and the disclosure of any concept in this section does not constitute an admission that said concept is prior art. Memory management is a form of resource management applied to computer memory. Some aspects of memory management provide dynamical allocation of portions of memory to programs at their request, and free the allocations for reuse when the portions of memory are no longer needed. Memory management provides important functionality for computer systems. However, improvements in memory management can be made with regards to high-performance computing and artificial intelligence (AI) systems. The disclosure relates generally to memory systems, and more particularly to thermal dissipation vias for stacked memory modules. SUMMARY In various embodiments, the systems and methods described herein include systems, methods, and apparatuses for thermal dissipation vias for stacked memory modules. In some aspects, the techniques described herein relate to a device including: a first through-silicon via (TSV) for heat dissipation routed vertically adjacent to at least one of a first stack of memory or a second stack of memory; and a second TSV for heat dissipation routed horizontally between at least one of: a physical layer (PHY) of the first stack of memory and a first memory die of the first stack of memory, or a PHY of the second stack of memory and a first memory die of the second stack of memory. In some aspects, the techniques described herein relate to a device, further including a third TSV routed horizontally between at least one of: the first memory die of the first stack of memory and a second memory die of the first stack of memory, or the first memory die of the second stack of memory and a second memory die of the second stack of memory. In some aspects, the techniques described herein relate to a device, wherein the first TSV connects to a first metal layer positioned above the first stack of memory and the second stack of memory. In some aspects, the techniques described herein relate to a device, wherein a heat sink is positioned on a top surface of the first metal layer. In some aspects, the techniques described herein relate to a device, wherein the first TSV connects to a second metal layer below the first stack of memory and the second stack of memory. In some aspects, the techniques described herein relate to a device, wherein the second metal layer is below at least one of the PHY of the first stack of memory or the PHY of the second stack of memory. In some aspects, the techniques described herein relate to a device, wherein the second TSV connects to at least one of a first metal sidewall adjacent to an outer surface of the first stack of memory or a second metal sidewall adjacent to an outer surface of the second stack of memory. In some aspects, the techniques described herein relate to a device, wherein the first TSV is routed between an inner surface of the first stack of memory and an inner surface of the second stack of memory. In some aspects, the techniques described herein relate to a device, wherein at least one of the first TSV or the second TSV is routed through a semiconductor that is deposited over at least one of the first stack of memory or the second stack of memory. In some aspects, the techniques described herein relate to a device, wherein the second TSV connects to the first TSV. In some aspects, the techniques described herein relate to a stacked integrated circuit (IC) device including: a first through-silicon via (TSV) for heat dissipation routed vertically adjacent to at least one of a first stack of dies or a second stack of dies; and a second TSV for heat dissipation routed horizontally between at least one of: a physical layer (PHY) of the first stack of dies and a first IC die of the first stack of dies, or a PHY of the second stack of dies and a first IC die of the second stack of dies. In some aspects, the techniques described herein relate to a stacked IC device, further including a third TSV routed horizontally between at least one of: the first IC die of the first stack of dies and a second IC die of the first stack of dies, or the first IC die of the second stack of dies and a second IC die of the second stack of dies. In some aspects, the techniques described herein relate to a stacked IC device, wherein the first TSV connects to a first metal layer positioned above the first stack of dies and the second stack of dies. In some aspects, the techniques described herein relate to a stacked IC device, wherein a heat sink is positioned on a top surface of the first metal layer. In some aspects, the techniques described herein relate to a stacked IC device, wherein the first TSV connects to a second metal layer below the first stack o