EP-4740027-A1 - METHOD AND SYSTEM FOR BOUNDARY SCAN TESTING OF JOINT TEST ACTION GROUP (JTAG) COMPLIANT DEVICES

EP4740027A1EP 4740027 A1EP4740027 A1EP 4740027A1EP-4740027-A1

Abstract

The present disclosure relates to a method and a system for boundary scan testing of joint test action group (JTAG)-compliant devices in massive multiple input and multiple output Radio Unit (MRU) The method comprises: (a) receiving, by receiving unit [302], a set of boundary scan description language (BSDL) files corresponding to JTAG-compliant devices; (b) determining, by determining unit [304], set of non-logical pins for each of the JTAG-compliant devices; (c) establishing, by processing unit [306], a daisy chain configuration; (d) categorizing, by processing unit [306], each of the JTAG-compliant devices into one of a passive device, a test device, and a logic device; (e) generating, by a generating unit [308], at least one test code based on the categorization and information associated with BSDL files; and (f) generating, by generating unit [308], a set of results after completion of execution of generated test code.

Inventors

GUPTA, DEEPAK
BHATNAGAR, PRADEEP KUMAR
BHATNAGAR, AAYUSH
KHOSYA, NEKIRAM
Sahoo, Satyajit

Assignees

Jio Platforms Limited

Dates

Publication Date: 20260513
Application Date: 20240705

Claims (14)

1. A method [400] for boundary scan testing of joint test action group (JTAG)-compliant devices in a massive multiple input and multiple output Radio Unit (MRU), the method [400] comprising: receiving, by a receiving unit [302], a set of boundary scan description language (BSDL) files corresponding to a set of JT AG-compliant devices; determining, by a determining unit [304], a set of non-logical pins for each of the set of JT AG-compliant devices within a JTAG tester; establishing, by a processing unit [306], a daisy chain configuration based on an information associated with the set of BSDL files and the determined set of non-logical pins; categorizing, by the processing unit [306], each of the set of JTAG-compliant devices in to at least one of a passive device, a test device, and a logic device; generating, by a generating unit [308], at least one test code based on the categorized set of JTAG-compliant devices and the information associated with the set of BSDL files; and generating, by the generating unit [308], a set of results after completion of execution of the generated at least one test code.
2. The method [400] as claimed in claim 1, further comprising: switching between a single JTAG chain configuration and the daisy chain configuration using a jumper that controls an enable pin of each of one or more level shifters, wherein in the single JTAG chain configuration, one or more pins of each Application-Specific Integrated Circuit (ASIC) of the JTAG compliant devices are connected to one or more individual JTAG connectors directly, and in the daisy chain configuration, a Test Data Output (TDO) pin of the ASIC is connected to a Test Data Input (TDI) pin of a subsequent ASIC of the daisy chain configuration.
3. The method [400] as claimed in claim 2, further comprising: connecting a plurality of peripheral devices to the ASIC via one or more interfaces, wherein the plurality of peripheral devices comprises, a memory device, an Ethernet PHY transceiver, a re-timer, a universal asynchronous receiver / transmitter (UART) connector, an Inter-Integrated Circuit (I2C) switch, a multiplexer, an I2C serial peripheral interface (SPI) bridge, a general-purpose input/output (GPIO) expander, a temperature sensor, a current sensor, a real-time clock, a microcontroller, an oscillator, a clock synchronizer, an analog-to-digital converter (ADC), a digital to analog converter (DAC), and a digital step attenuator (DSA).
4. The method [400] as claimed in claim 3, wherein the one or more interfaces for connecting peripheral devices comprise at least one from among an Inter-Integrated Circuit (I2C), a serial peripheral interface (SPI), a Peripheral Component Interconnect Express (PCIe), a reduced gigabit media independent interface (RGMII), one or more high-speed interconnects, or any combination thereof.
5. The method [400] as claimed in claim 1, comprising: performing one or more additional tests related to reading/writing registers, measuring voltages or currents, checking temperature sensors, or verifying manufacture IDs.
6. The method [400] as claimed in claim 1, wherein the test codes are generated based on one of: using a library of test files, and a template stored in a database.
7. A system [300] for boundary scan testing of joint test action group (JTAG)-compliant devices in a massive Radio Unit (MRU), the system [300] comprises: a receiving unit [302] configured to receive a set of boundary scan description language (BSDL) files corresponding to a set of JT AG-compliant devices; a determining unit [304] connected to at least the receiving unit [302], the determining unit [304] configured to determine a set of non-logical pins for each of the set of JT AG- compliant devices within a JTAG tester; a processing unit [306] connected to at least the determining unit [304], the processing unit [306] configured to establish a daisy chain configuration based on an information associated with the set of BSDL files and the determined set of non-logical pins; the processing unit [306] connected to at least the determining unit [304], the processing unit [306] configured to categorize each of the set of JT AG-compliant devices in to at least one of a passive device, a test device, and a logic device; a generating unit [308] connected to at least the processing unit [306], the generating unit [308] configured to generate at least one test code based on the categorized set of JTAG- compliant devices and the information associated with the set of BSDL files; and the generating unit [308] connected to at least the processing unit [306], the generating unit [308] configured to generate a set of results after completion of execution of the generated at least one test code.
8. The system [300] as claimed in claim 7, wherein the processing unit [306] is further configured to switch between a single JTAG chain configuration and the daisy chain configuration using a jumper that controls an enable pin of each of one or more level shifters, wherein in the single JTAG chain configuration, one or more pins of each Application- Specific Integrated Circuit (ASIC) of the JTAG compliant devices are connected to one or more individual JTAG connectors directly, and in the daisy chain configuration, a Test Data Output (TDO) pin of the ASIC is connected to a Test Data Input (TDI) pin of a subsequent ASIC of the daisy chain configuration.
9. The system [300] as claimed in claim 8, wherein the processing unit [306] is further configured to connect a plurality of peripheral devices to the ASIC via one or more interfaces, wherein the plurality of peripheral devices comprises a memory device, an Ethernet PHY transceiver, a re-timer, a universal asynchronous receiver / transmitter (UART) connector, an inter-integrated circuit (I2C) switch, a multiplexer, I2C serial peripheral interface (SPI) bridge, a general-purpose input/output (GPIO) expander, a temperature sensor, a current sensor, a real-time clock, a microcontroller, an oscillator, a clock synchronizer, an analog-to digital converter (ADC), a digital to analog converter (DAC), and a digital step attenuator (DSA).
10. The system [300] as claimed in claim 9, wherein the one or more interfaces for connecting peripheral devices comprise at least one from among an Inter-Integrated Circuit (I2C), a serial peripheral interface (SPI), a Peripheral Component Interconnect Express (PCIe), a reduced gigabit media independent interface (RGMII), one or more high-speed interconnects, or any combination thereof.
11. The system [300] as claimed in claim 7, wherein the processing unit [306] is configured to perform one or more additional tests related to reading/writing registers, measuring voltages or currents, checking temperature sensors, or verifying manufacture IDs.
12. The system [300] as claimed in claim 7, wherein the test codes are generated based on one of: using a library of test files, and a template stored in a database.
13. A user equipment in communication with a system [300] for boundary scan testing of joint test action group (JTAG)-compliant devices in a massive MIMO Radio Unit (MRU), the user equipment comprising at least: a user interface configured to receive a set of results related to the boundary scan testing of the JTAG-compliant devices, wherein the set of results is generated by the system [300] based on: receiving, by a receiving unit [302] via JTAG tester, a set of boundary scan description language (BSDL) files corresponding to a set of JTAG-compliant devices; determining, by a determining unit [304], a set of non-logical pins for each of the set of JTAG-compliant devices within a JTAG tester; establishing, by a processing unit [306], a daisy chain configuration based on an information associated with the set of BSDL files and the determined set of non-logical pins; categorizing, by the processing unit [306], each of the set of JTAG-compliant devices in to at least one of a passive device, a test device, and a logic device; generating, by a generating unit [308], at least one test code based on the categorized set of JTAG-compliant devices and the information associated with the set of BSDL files; and generating, by the generating unit [308], the set of results after completion of execution of the generated at least one test code.
14. A non-transitory computer readable storage medium storing instructions for boundary scan testing of joint test action group (JTAG)-compliant devices in a massive multiple input and multiple output (MIMO) Radio Unit (MRU), the instructions include executable code which, when executed by one or more units of a system [300], causes: a receiving unit [302] of the system [300] to receive a set of boundary scan description language (BSDL) files corresponding to a set of JTAG-compliant devices; a determining unit [304] of the system [300] to determine a set of non-logical pins for each of the set of JTAG-compliant devices within a JTAG tester; a processing unit [306] of the system [300] to establish a daisy chain configuration based on an information associated with the set of BSDL files and the determined set of non-logical pins; - the processing unit [306] of the system [300] further to categorize each of the set of JTAG-compliant devices in to at least one of a passive device, a test device, and a logic device; a generating unit [308] of the system [300] to generate at least one test code based on the categorized set of JTAG-compliant devices and the information associated with the set of B SDL files; and - the generating unit [308] of the system [300] further to generate a set of results after completion of execution of the generated at least one test code.

Description

METHOD AND SYSTEM FOR BOUNDARY SCAN TESTING OF JOINT TEST ACTION GROUP (JTAG) COMPLIANT DEVICES FIELD OF INVENTION [0001] Embodiments of the present disclosure generally relate to testing of electronic components. More particularly, embodiments of the present disclosure relate to a method and system for boundary scan testing of joint test action group (JTAG)-compliant devices in a massive multiple input and multiple output Radio Unit (MRU). BACKGROUND OF THE DISCLOSURE [0002] The following description of the related art is intended to provide background information pertaining to the field of the disclosure. This section may include certain aspects of the art that may be related to various features of the present disclosure. However, it should be appreciated that this section is used only to enhance the understanding of the reader with respect to the present disclosure, and not as admissions of the prior art. [0003] Wireless communication systems and other systems also employ various electronic components such as processor, integrated circuits, etc. A typical radio unit may comprise a printed circuit board (PCB) and a mix of integrated circuits (ICs) of different packages and footprints. Assembly issues in PCB manufacturing, such as open circuits, shorts, and incorrect component placements, can lead to product failures and costly rework. Therefore, testing and debugging of electronic components is essential to ensure the quality, reliability, and safety of these electronic devices. Existing solutions related to testing the electronic components require physical access to each test point on the board, which is a tedious, time-consuming, and labour-intensive process. This not only increases the cost of production but also delays the manufacturing process significantly. Due to the necessity of physical access for each test point, these traditional methods are not able to provide comprehensive coverage of all components and interconnections on the board, especially when it comes to intricate and complex ICs (Integrated Circuits). This may lead to some faults going undetected, potentially causing product failures later on. When a product failure does occur, especially after deployment, identifying the source of the problem can be extremely time-consuming due to the lack of comprehensive pre-deployment testing. This lengthy debugging process can further increase costs in terms of labour and downtime. Further, existing methods can lead to high Mean Time to Repair (MTTR) due to inefficient testing and debugging mechanisms. [0004] JTAG (Joint Test Action Group) refers to a standard for testing and debugging electronic devices, particularly integrated circuits and printed circuit boards. It is commonly used in the development and production of electronic devices to verify and test hardware components. It enables features like boundary scan testing, which can test the interconnections between integrated circuits on a PCB without the need for functional test access points (i.e., physical or logical points on a device or system where test signals can be applied, and responses are obtained to observe during functional testing). That is, the JTAG testing enables to determine the assembly defect for any active component in PCB without waiting for their functional testing. For the testing and debugging of the components employed in the wireless communication systems and to ensure the performance and reliability requirements, JTAG can be used during development and manufacturing. Boundary scan is a test technique that involves devices designed with shift registers placed between each device pin and an internal logic. Each shift register is called a boundary scan cell. These boundary scan cells allow to control and observe what happens at each input and output pin. In order to run boundary scan testing it is necessary to have some information about the implementation of JTAG on the enabled devices on a board. This information comes from the BSDL (Boundary Scan Description Language) files for these devices. BSDL files are text files that describe the boundary scan architecture and behaviour of a digital integrated circuit (IC) or component. Thus, a JTAG / boundary scan test, unlike functional test, provides high precision fault information to help with rapid repair. Furthermore, JTAG testing also provides the capability to view both the physical location of a fault on the layout of the board and the logical design of the area of the circuit in which the fault exists on the schematic. [0005] As discussed above, the traditional testing methods require physical access to test points, and the detection and diagnosis of these issues is time-consuming and labour-intensive. Moreover, the existing solutions also failed to perform JTAG testing on the intricate and complex ICs (Integrated Circuits) in an efficient and effective manner. The JTAG testing offered by the existing solutions is not able to provide comprehensive coverage of J