EP-4740083-A1 - POWER OPTIMIZATION FOR CAMERA DEVICES

Abstract

Aspects presented herein relate to methods and devices for data processing including an apparatus, e.g., a CPU. The apparatus may obtain an indication of a set of sensors that are connected to at least one clock source at a device. The apparatus may also detect whether each of the set of sensors is an active sensor or an inactive sensor. Further, the apparatus may select a clock configuration for a set of hardware components at the device based on the detection of whether each of the set of sensors is the active sensor or the inactive sensor, where the clock configuration is associated with the at least one clock source. The apparatus may also output an indication of the selected clock configuration for the set of hardware components at the device.

Inventors

• KEDIYA, Alok
• PODDAR, MANISH
• VANKADARA, SURESH
• MITTAL, Mukund
• GAGRANI, GAURAV

Assignees

• QUALCOMM INCORPORATED

Dates

Publication Date

20260513

Application Date

20240520

Claims (20)

1. 1. An apparatus for data processing, comprising: at least one memory; and at least one processor coupled to the at least one memory and, based at least in part on information stored in the at least one memory, the at least one processor, individually or in any combination, is configured to: obtain an indication of a set of sensors that are connected to at least one clock source at a device; detect whether each of the set of sensors is an active sensor or an inactive sensor; select a clock configuration for a set of hardware components at the device based on the detection of whether each of the set of sensors is the active sensor or the inactive sensor, wherein the clock configuration is associated with the at least one clock source; and output an indication of the selected clock configuration for the set of hardware components at the device.
2. 2. The apparatus of claim 1, wherein the at least one processor, individually or in any combination, is further configured to: set a clock control for each of the set of hardware components based on the selected clock configuration, wherein the clock control is associated with the at least one clock source.
3. 3. The apparatus of claim 2, wherein the at least one processor, individually or in any combination, is further configured to: receive an indication of a clock for each of the set of hardware components prior to the set of the clock control for each of the set of hardware components, wherein the clock is associated with the at least one clock source; and transmit an indication of the at least one clock source for each of the set of hardware components subsequent to the set of the clock control for each of the set of hardware components.
4. 4. The apparatus of claim 3, wherein to set the clock control for each of the set of hardware components, the at least one processor, individually or in any combination, is configured to: enable a logic of the clock for each of the set of hardware components.
5. 5. The apparatus of claim 1, wherein the active sensor is associated with at least one of actively streaming data or leaking voltage, and wherein the inactive sensor is associated with at least one of being powered off or not actively streaming data.
6. 6. The apparatus of claim 1, wherein to select the clock configuration, the at least one processor, individually or in any combination, is configured to: select the clock configuration based on a certain sensor in the set of sensors being the active sensor.
7. 7. The apparatus of claim 1, wherein the at least one processor, individually or in any combination, is further configured to: write, if a certain sensor in the set of sensors is the inactive sensor, an indication to not provide a clock for the at least one clock source.
8. 8. The apparatus of claim 1, wherein the at least one clock source is a shared clock source, a shared voltage source, or a shared clock and voltage source.
9. 9. The apparatus of claim 1, wherein each of the set of sensors is at least one of: a data transmitter, a camera sensor, a component sensor, or a microphone.
10. 10. The apparatus of claim 9, wherein the device is a camera, and wherein each of the set of sensors is the camera sensor.
11. 11. The apparatus of claim 1, wherein the clock configuration is a hardware clock control configuration of the at least one clock source.
12. 12. The apparatus of claim 11, wherein the hardware clock control configuration is configured to be enabled or disabled based on a software configuration for the device.
13. 13. The apparatus of claim 1, wherein the set of hardware components includes at least one of: a camera serial interface physical layer (CSI-PHY), a camera serial interface decoder (CSID), an image signal processor (ISP), or an ISP front engine (IFE).
14. 14. The apparatus of claim 1, wherein the clock configuration is a shared clock configuration or a shared voltage configuration for each of the set of hardware components, wherein the at least one clock source is a shared clock source or a shared voltage source.
15. 15. The apparatus of claim 1, wherein to output the indication of the selected clock configuration, the at least one processor, individually or in any combination, is configured to: transmit the indication of the selected clock configuration for the set of hardware components at the device.
16. 16. The apparatus of claim 15, further comprising at least one of an antenna or a transceiver coupled to the at least one processor, wherein to transmit the indication of the selected clock configuration, the at least one processor, individually or in any combination, is further configured to: transmit, via at least one of the antenna or the transceiver, the indication of the selected clock configuration to a hardware controller.
17. 17. The apparatus of claim 1, wherein to output the indication of the selected clock configuration, the at least one processor, individually or in any combination, is further configured to: store the indication of the selected clock configuration for the set of hardware components at the device.
18. 18. The apparatus of claim 17, wherein to store the indication of the selected clock configuration, the at least one processor, individually or in any combination, is configured to: store the indication of the selected clock configuration at a hardware register or a hardware memory.
19. 19. A method of data processing, comprising: obtaining an indication of a set of sensors that are connected to at least one clock source at a device; detecting whether each of the set of sensors is an active sensor or an inactive sensor; selecting a clock configuration for a set of hardware components at the device based on the detection of whether each of the set of sensors is the active sensor or the inactive sensor, wherein the clock configuration is associated with the at least one clock source; and outputting an indication of the selected clock configuration for the set of hardware components at the device.
20. 20. The method of claim 19, further comprising: setting a clock control for each of the set of hardware components based on the selected clock configuration, wherein the clock control is associated with the at least one clock source.

Description

POWER OPTIMIZATION FOR CAMERA DEVICES CROSS-REFERENCE TO RELATED APPLICATION [0001] This application claims the benefit of U.S. Non-Provisional Patent Application Serial No. 18/349,082, entitled “POWER OPTIMIZATION FOR CAMERA DEVICES” and filed on July 7, 2023, which is expressly incorporated by reference herein in its entirety. TECHNICAL FIELD [0002] The present disclosure relates generally to processing systems and, more particularly, to one or more techniques for graphics and data processing. INTRODUCTION [0003] Computing devices often perform graphics and/or display processing (e.g., utilizing a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices may include, for example, computer workstations, mobile phones such as smartphones, embedded systems, personal computers, tablet computers, and video game consoles. GPUs are configured to execute a graphics processing pipeline that includes one or more processing stages, which operate together to execute graphics processing commands and output a frame. A central processing unit (CPU) may control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern day CPUs are typically capable of executing multiple applications concurrently, each of which may need to utilize the GPU during execution. A display processor is configured to convert digital information received from a CPU to analog values and may issue commands to a display panel for displaying the visual content. A device that provides content for visual presentation on a display may utilize a GPU and/or a display processor. [0004] A GPU of a device may be configured to perform the processes in a graphics processing pipeline. Further, a display processor or display processing unit (DPU) may be configured to perform the processes of display processing. However, with the advent of wireless communication and smaller, handheld devices, there has developed an increased need for improved graphics or data processing. BRIEF SUMMARY [0005] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later. [0006] In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a central processing unit (CPU), a display processing unit (DPU), a graphics processing unit (GPU), or any apparatus that may perform display processing. The apparatus may obtain an indication of a set of sensors that are connected to at least one clock source at a device. The apparatus may also detect whether each of the set of sensors is an active sensor or an inactive sensor. Additionally, the apparatus may write, if a certain sensor in the set of sensors is the inactive sensor, an indication to not provide a clock for the at least one clock source. The apparatus may also select a clock configuration for a set of hardware components at the device based on the detection of whether each of the set of sensors is the active sensor or the inactive sensor, where the clock configuration is associated with the at least one clock source. Moreover, the apparatus may receive an indication of a clock for each of the set of hardware components prior to setting the clock control for each of the set of hardware components, where the clock is associated with the at least one clock source. The apparatus may also set a clock control for each of the set of hardware components based on the selected clock configuration, where the clock control is associated with the at least one clock source. The apparatus may also transmit an indication of the at least one clock source for each of the set of hardware components subsequent to setting the clock control for each of the set of hardware components. Further, the apparatus may output an indication of the selected clock configuration for the set of hardware components at the device. [0007] The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS [0008] FIG. l is a block diagram that illustrates an example content generation system. [0009] FIG. 2 illustrates an example graphics processing unit (GPU). [0010] FIG. 3 illustrates an example display framework including a display processor and a display. [0011] FIG. 4 is a diagram illustrating an example communication of content/data in accordance wit