EP-4740088-A1 - DATA PROTECTION WITH TIME-VARYING IN-SITU DATA REFRESH

EP4740088A1EP 4740088 A1EP4740088 A1EP 4740088A1EP-4740088-A1

Abstract

A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including storing a set of user data and multiple portions of error correction data. The operations can also include, responsive to an expiration of a first threshold amount of time after storing the set of user data, performing, using the third portion of the error correction data, a first error correction operation, on each of the set of user data, the first portion, and the second portion, and rewriting, on the memory device, the set of user data, the first portion, and the second portion. The operations can further include deleting the third portion.

Inventors

NGUYEN, DUNG VIET
FITZPATRICK, JAMES
TSENG, HUAI-YUAN

Assignees

Micron Technology, Inc.

Dates

Publication Date: 20260513
Application Date: 20240626

Claims (20)

1. A system comprising: a memory device comprising an array of memory cells arranged into one or more management units (MUs), wherein each memory cell in the array of memory cells is respectively connected to a corresponding wordline of a plurality of wordlines; and a processing device, operatively coupled with the memory device, to perform operations comprising: storing, on the memory device, a set of user data and a plurality of portions of error correction data, wherein a first portion of the plurality of portions of error correction data is stored in a first set of MUs of the memory device, a second portion of the plurality of portions of error correction data is stored in a second set of MUs of the memory device, and a third portion of the plurality of portions of error correction data is stored in a third set of MUs of the memory device; responsive to an expiration of a first threshold amount of time after storing the set of user data: performing, using the third portion of the error correction data, a first error correction operation, on the set of user data, the first portion, and the second portion; and rewriting, on the memory device, the set of user data, the first portion, and the second portion; and deleting the third portion.
2. The system of claim 1, wherein the processing device is to perform further operations comprising: responsive to an expiration of a second threshold amount of time after storing the set of user data: performing, using the second portion of the error correction data, a second error correction operation on each of the set of user data and the first portion; rewriting, on the memory device, the set of user data and the first portion; and deleting the second portion.
3. The system of claim 2, wherein performing error correction comprises: retrieving the set of user data; retrieving one or more portions of error correction data; correcting one or more errors in the set of user data by using the one or more portions of error correction data; and correcting one or more errors in the one or more portions of error correction data by using the set of user data, at least one portion of error correction data, or a combination of the set of user data and the at least one portion of error correction data.
4. The system of claim 2, wherein the first set of MUs comprises: a first set of memory cells that store the set of user data, and a second set of memory cells that store the first portion of error correction data, wherein both the first set of memory cells and the second set of memory cells are connected to a same wordline of the plurality of wordlines.
5. The system of claim 1, wherein the plurality of portions of error correction data comprises at least two different types of error correction data, each type of error correction data selected from parity data, target threshold voltage indication data, and duplicate data, and wherein each portion of error correction data comprises a single type of data.
6. The system of claim 1, wherein the plurality of portions of error correction data comprises a local portion and a remote portion, wherein the local portion is stored in the first set of MUs, the first set of MUs comprising the set of user data, and wherein the remote portion is stored in the second set of MUs or the third set of MUs.
7. The system of claim 1, wherein the first threshold amount of time depends on a total amount of error correction data in the plurality of portions of error correction data.
8. A method comprising: storing a set of user data, on a memory device comprising an array of memory cells arranged into one or more management units (MUs), each memory cell respectively connected to a corresponding wordline of a plurality of wordlines; storing, on the memory device, a plurality of portions of error correction data, wherein a first portion of the of the plurality of portions of error correction data is stored in a first set of MUs of the memory device, a second portion of the plurality of portions of error correction data is stored in a second set of MUs of the memory device, and a third portion of the plurality of portions of error correction data is stored in a third set of MUs of the memory device; responsive to an expiration of a first threshold amount of time after storing the set of user data: performing, using the third portion of the error correction data, a first error correction operation on the set of user data, the first portion of error correction data, and the second portion of error correction data; and rewriting, on the memory device, the set of user data, the first portion of error correction data, and the second portion of error correction data; and deleting the third portion of error correction data.
9. The method of claim 8, further comprising: responsive to an expiration of a second threshold amount of time after storing the set of user data: performing, using the second portion of the error correction data, a second error correction operation on the set of user data and the first portion of error correction data; rewriting, on the memory device, the set of user data and the first portion of error correction data; and deleting the second portion of error correction data.
10. The method of claim 9, wherein performing error correction comprises: retrieving the set of user data; retrieving one or more portions of error correction data; correcting one or more errors in the set of user data by using the one or more portions of error correction data; and correcting one or more errors in the one or more portions of error correction data by using the set of user data, at least one portion of error correction data, or a combination of the set of user data and the at least one portion of error correction data.
11. The method of claim 8, wherein the first set of management units comprises: a first set of memory cells that store the set of user data, and a second set of memory cells that store the first portion of error correction data, wherein both the first set of memory cells and the second set of memory cells are connected to a same wordline of the plurality of wordlines.
12. The method of claim 8, wherein the plurality of portions of error correction data comprises at least two different types of error correction data, each type of error correction data selected from parity data, target threshold voltage indication data, and duplicate data, and wherein each portion of error correction data comprises a single type of data.
13. The method of claim 8, wherein the plurality of portions of error correction data comprises a local portion of error correction data and a remote portion of error correction data, wherein the local portion of error correction data is stored in the first set of MUs, the first set of MUs comprising the set of user data, and wherein the remote portion of error correction data is stored in the second set of MUs or the third set of MUs.
14. The method of claim 8, wherein the first threshold amount of time depends on a total amount of correction data in the plurality of portions of error correction data.
15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: writing a set of user data in a first location on a memory device, the memory device comprising an array of memory cells arranged into one or more management units, each memory cell respectively connected to a corresponding wordline of a plurality of wordlines; writing, in a first set of locations on the memory device, a set of portions of error correction data associated with the set of user data, each respective portion of error correction data being written in a corresponding location of the first set of locations; responsive to an expiration of a first threshold amount of time relative to writing the set of user data: regenerating, using a first portion of error correction data, the set of user data and one or more remaining portions of error correction data; rewriting, in the first location, the set of user data; and rewriting each respective remaining portion of error correction data in the corresponding location of the first set of locations; and marking the first portion of error correction data as invalidated to allow erasure of the first portion of error correction data.
16. The non-transitory computer-readable storage medium of claim 15, wherein the instructions cause the processing device to perform the operations further comprising: erasing the first portion of error correction data.
17. The non-transitory computer-readable storage medium of claim 16, wherein the instructions cause the processing device to perform the operations further comprising: responsive to an expiration of a second threshold amount of time relative to writing the set of data: regenerating, using a second portion of error correction data, the set of user data and the one or more remaining portions of error correction data; rewriting, in the first location, the set of user data; and rewriting, in a second set of locations on the memory device, the one or more remaining portions of error correction data, each respective remaining portion of error correction data being rewritten in the corresponding location of the second set of locations; and marking the second portion of error correction data as invalidated to allow erasure of the second portion of error correction data.
18. The non-transitory computer-readable storage medium of claim 15, wherein regenerating the set of user data and one or more remaining portions of error correction data comprises: retrieving the set of user data from the first location; retrieving one or more portions of error correction data, wherein the one or more portions of error correction data comprise the first portion of error correction data; correcting one or more errors in the set of user data by using the one or more portions of error correction data; and correcting one or more errors in the one or more portions of error correction data by using the set of user data, the first portion of error correction data, or a combination of the set of user data and the first portion of error correction data.
19. The non-transitory computer-readable storage medium of claim 15, wherein the set of portions of error correction data comprises at least two different types of error correction data, each type of error correction data selected from parity data, threshold voltage indication data, and duplicate data, and wherein each portion of error correction data comprises a single type of data.
20. The non-transitory computer-readable storage medium of claim 15, wherein the set of portions of error correction data comprises a local portion of error correction data and a remote portion of error correction data, wherein the local portion of error correction data is written to a first management unit, the first management unit comprising the set of user data, and wherein the remote portion of error correction data is written to a second management unit that is in a different location than the first management unit on the memory device.

Description

DATA PROTECTION WITH TIME-VARYING IN-SITU DATA REFRESH TECHNICAL FIELD [001] Embodiments of the disclosure relate generally to memory sub-systems, and more specifically, relate to managing refreshing of data on memory devices. BACKGROUND [002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. In general, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices. BRIEF DESCRIPTION OF THE DRAWINGS [003] The disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. The drawings, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only. [004] FIG. 1 illustrates an example computing system that includes a memory subsystem in accordance with some embodiments of the present disclosure; [005] FIG. 2 is a schematic diagram of multiple example data layouts on a memory device in accordance with some embodiments of the present disclosure; [006] FIG. 3 depicts a graph of a read window budget (RWB) as a function of data retention time on a memory device in accordance with some embodiments of the present disclosure; [007] FIG. 4 is a flow diagram of an example method for performing time-varying in- situ data refresh management on memory devices in accordance with some embodiments of the present disclosure; [008] FIG. 5A is a flow diagram of an example method for performing time-varying in- situ data refresh on memory devices in accordance with some embodiments of the present disclosure; [009] FIG. 5B is a flow diagram of an example method for performing error correction on memory devices in accordance with some embodiments of the present disclosure; [010] FIG. 6 is a flow diagram of an example method for performing time-varying in- situ data refresh on memory devices in accordance with some embodiments of the present disclosure; and [011] FIG. 7 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION [012] Aspects of the present disclosure are directed to managing time-varying in-situ refreshing of data on memory devices. A memory sub-system can be a storage device, a memory module, or a combination of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction with FIG. 1. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory subsystem. [013] A memory sub-system can include high density non-volatile memory devices where retention of data is desired when no power is supplied to the memory device. One example of non-volatile memory devices is a negative-and (NAND) memory device. Other examples of non-volatile memory devices are described below in conjunction with FIG. 1. A non-volatile memory device is a package of one or more dies. Each die can include of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane includes of a set of physical blocks. Each block includes of a set of pages. Each page includes of a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information, and has various logic states that correlate to the number of bits being stored. The logic states can be represented by binary values, such as “0” and “1”, or combinations of such values. [014] A memory device can include cells arranged in a two-dimensional or three- dimensional grid. Memory cells can be formed on a silicon wafer in an array of columns connected by conductive lines (also hereinafter referred to as strings, bitlines, or BLs) and rows connected by conductive lines (also hereinafter referred to as wordlines or WLs). A wordline can refer to a conductive line that connects control gates of a set (e.g., one or more rows) of memory cells of a memory device that are used with one or more bitlines to generate the address of each of the memory cells. In some embodiments, each plane can carry an array of memory cells formed onto a silicon wafer and joined by conductive BLs and WLs, such that a wordline joins multiple memory cells forming a row of the array of memory cells, while a bitline joins multiple memory cells forming a column of the array of memory cells. The intersection of a bitline and wordline constitutes the address of the memory cell. A block hereinafter refers to a unit of the memory device used to store data and can include a group of memory cells, a wordline group, a wordline, or individual