EP-4740091-A1 - HINTS IN A DATA PROCESSING APPARATUS

Abstract

An apparatus is described having decoding circuitry that is responsive to a sequence of instructions to generate control signals, data processing circuitry comprising data processing functional hardware, and a plurality of registers. The data processing circuitry is responsive to the control signals to operate the data processing functional hardware in an operating procedure to perform data processing operations defined by the sequence of instructions, using data stored in the plurality of registers, to produce data processing results. The decoding circuitry is responsive to a register identifying hint instruction preceding the sequence of instructions to generate hint metadata in dependence on at least one register identified by the register identifying hint instruction. The data processing circuitry is arranged, when the hint metadata is present, to be responsive to the control signals to operate the data processing functional hardware in a modified operating procedure to perform the data processing operations defined by the sequence of instructions to produce the data processing results, where the modified operating procedure differs from the operating procedure by implementing one or more performance measures in dependence on the hint metadata.

Inventors

• GROCUTT, Thomas Christopher

Assignees

• ARM Limited

Dates

Publication Date

20260513

Application Date

20240528

Claims (20)

1. 1. Apparatus comprising: decoding circuitry to decode instructions, wherein the decoding circuitry is responsive to a sequence of instructions to generate control signals; data processing circuitry comprising data processing functional hardware; and a plurality of registers; wherein the data processing circuitry is responsive to the control signals to operate the data processing functional hardware in an operating procedure to perform data processing operations defined by the sequence of instructions, using data stored in the plurality of registers, to produce data processing results; wherein: the decoding circuitry is responsive to a register identifying hint instruction preceding the sequence of instructions to generate hint metadata in dependence on at least one register identified by the register identifying hint instruction; the data processing circuitry is arranged, when the hint metadata is present, to be responsive to the control signals to operate the data processing functional hardware in a modified operating procedure to perform the data processing operations defined by the sequence of instructions to produce the data processing results; and the modified operating procedure differs from the operating procedure by implementing one or more performance measures in dependence on the hint metadata.
2. 2. An apparatus as claimed in Claim 1 , wherein at least one of the one or more performance measures is implemented in association with performing one or more data processing operations defined by one or more given instructions in the sequence of instructions that accesses a given register identified by the register identifying hint instruction.
3. 3. An apparatus as claimed in Claim 2, wherein the one or more given instructions are instructions that use a value held in the given register in a predetermined manner.
4. 4. An apparatus as claimed in Claim 2 or Claim 3, wherein the one or more given instructions are instructions of a predetermined type.
5. 5. An apparatus as claimed in any preceding claim, wherein at least one of the one or more performance measures is implemented in response to generation of the hint metadata
6. 6. An apparatus as claimed in any preceding claim, further comprising: hint metadata storage associated with the plurality of registers; and hint metadata processing circuitry to store the hint metadata in the hint metadata storage; wherein the data processing circuitry is arranged to access the hint metadata storage in order to determine, for a specified register, whether that specified register has hint metadata associated therewith.
7. 7. An apparatus as claimed in Claim 6, wherein the hint metadata storage comprises a metadata field provided for each register, into which any associated hint metadata is stored by the hint metadata processing circuitry.
8. 8. An apparatus as claimed in Claim 6 or Claim 7 when dependent on claim 2, wherein when the data processing functional hardware performs the one or more data processing operations defined by the one or more given instructions, the one or more given instructions identifying the given register causes the hint metadata for the given register to be accessed and the at least one performance measure to be implemented.
9. 9. An apparatus as claimed in any of claims 1 to 5, further comprising hint control circuitry provided in association with the decoding circuitry to store the hint metadata, and to determine when to trigger each of the one or more performance measures.
10. 10. An apparatus as claimed in Claim 9 when dependent on Claim 2, wherein: when the one or more given instructions is decoded, the hint control circuitry is arranged to cause at least one performance modifying control signal to be issued in association with one or more control signals generated by the decoding circuitry to identify the one or more data processing operations defined by the one or more given instructions; and when the data processing functional hardware performs the one or more data processing operations, the at least one performance modifying control signal triggers the at least one performance measure to be implemented.
11. 11. An apparatus as claimed in any preceding claim, wherein the decoding circuitry is responsive to a further register identifying hint instruction to generate further hint metadata indicative of at least one register identified by the further register identifying hint instruction.
12. 12. An apparatus as claimed in Claim 11 , wherein the further hint metadata is arranged to supplement the hint metadata.
13. 13. An apparatus as claimed in Claim 11 , wherein when the further register identifying hint instruction incorporates an append flag, the further hint metadata is arranged to supplement the hint metadata, whilst in the absence of the append flag the generation of the further hint metadata causes the hint metadata to be cleared.
14. 14. An apparatus as claimed in any preceding claim, wherein the decoding circuitry is responsive to a register hint clear instruction to clear the hint metadata associated with each register identified by the register hint clear instruction.
15. 15. An apparatus as claimed in any preceding claim, wherein the decode circuitry is responsive to a register hint clear all instruction to clear all existing hint metadata.
16. 16. An apparatus as claimed in any preceding claim, wherein the hint metadata associated with at least a given register is cleared in response to detection of one or more events.
17. 17. An apparatus as claimed in Claim 16, wherein the one or more events comprise one or more of: taking of an exception; transition between different software functions; identification of an end of a loop for which the hint metadata is intended to be used; execution of an instruction of a predetermined type that causes at least a given type of access to be performed to the given register.
18. 18. An apparatus as claimed in any preceding claim, wherein the register identifying hint instruction specifies a hint type.
19. 19. An apparatus as claimed in Claim 18, wherein the register identifying hint instruction comprises a hint type vector identifying which of plural hint types the hint metadata is to be generated for.
20. 20. An apparatus as claimed in Claim 19, wherein for each hint type specified in the hint type vector, the register identifying hint instruction is arranged to identify one or more registers to be associated with that hint type.

Description

HINTS IN A DATA PROCESSING APPARATUS BACKGROUND The present disclosure relates to data processing. In particular, the present disclosure relates to providing operational hints in a data processing apparatus. A data processing apparatus is caused to carry out selected data processing operations by being provided with a sequence of instructions defining what those data processing operations should be. The instructions must be predefined for a data processing apparatus, this collection of predefined instructions commonly being referred to as its “instruction set”. It is, on the one hand, useful for a data processing apparatus to be able to perform many defined data processing operations, but on the other hand this comes at the cost of a corresponding large number of instructions needing to be defined as part of its instruction set. Moreover, where the instructions defined for the instruction set are specified within a limited number of bits, this in turn limits the number of individual instructions which can be defined, and therefore for an instruction to be defined for a given data processing operation requires justification for the use of that “instruction space” within the instruction set. Consequently the number of individual data processing operations for which instructions may be defined is limited. This imposes a constraint on the ability of the programmer of the data processing apparatus to define the data processing operations which it should perform in a concise number of data processing instructions. SUMMARY In one example arrangement there is provided an apparatus comprising: decoding circuitry to decode instructions, wherein the decoding circuitry is responsive to a sequence of instructions to generate control signals; data processing circuitry comprising data processing functional hardware; and a plurality of registers; wherein the data processing circuitry is responsive to the control signals to operate the data processing functional hardware in an operating procedure to perform data processing operations defined by the sequence of instructions, using data stored in the plurality of registers, to produce data processing results; wherein: the decoding circuitry is responsive to a register identifying hint instruction preceding the sequence of instructions to generate hint metadata in dependence on at least one register identified by the register identifying hint instruction; the data processing circuitry is arranged, when the hint metadata is present, to be responsive to the control signals to operate the data processing functional hardware in a modified operating procedure to perform the data processing operations defined by the sequence of instructions to produce the data processing results; and the modified operating procedure differs from the operating procedure by implementing one or more performance measures in dependence on the hint metadata. In another example arrangement, there is provided a computer-readable medium to store computer-readable code for fabrication of the apparatus mentioned above. In a yet further example arrangement there is provided a method of modifying an operating procedure of a data processing apparatus, comprising: decoding a sequence of instructions to generate control signals; operating data processing functional hardware, in response to the control signals, in an operating procedure to perform data processing operations defined by the sequence of instructions, using data stored in a plurality of registers, to produce data processing results; generating, in response to a register identifying hint instruction preceding the sequence of instructions, hint metadata in dependence on at least one register identified by the register identifying hint instruction; and when the hint metadata is present, operating the data processing functional hardware, in response to the control signals, in a modified operating procedure to perform the data processing operations defined by the sequence of instructions to produce the data processing results, wherein the modified operating procedure differs from the operating procedure by implementing one or more performance measures in dependence on the hint metadata. In a still further example arrangement there is provided a computer program comprising instructions which, when executed by a host data processing apparatus, control the host data processing apparatus to provide an instruction execution environment for executing target program code, the computer program comprising: instruction decoding program logic to decode instructions, wherein the instruction decoding program logic is responsive to a sequence of instructions to generate control signals; data processing program logic to simulate data processing functional hardware; and register simulating program logic to maintain register emulating data structures to emulate a plurality of registers; wherein the data processing program logic is responsive to the control signals to oper