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EP-4740144-A2 - GENERATION AND COMPILATION OF REPRESENTATIONS OF FAULT TOLERANT QUANTUM CIRCUITS

EP4740144A2EP 4740144 A2EP4740144 A2EP 4740144A2EP-4740144-A2

Abstract

One example aspect of the present disclosure is directed to a method for implementing fault-tolerant quantum computing. The method includes receiving a set of inputs for a fault-tolerant quantum-computation circuit (QCC). The set of inputs includes an indication of a set of logical qubits and an indication of a set of quantum-logic stabilizers that the QCC is configured to perform on the set of logical qubits. A satisfiability modulo theory (SMT) model for the QCC is generated based on the set of inputs. The SMT model includes a set of constraints. A set of values to populate a data structure. The set of values satisfies the set of constraints of the SMT model. The data structure populated by the set of values encodes an intermediate representation (IR) of a time evolution of the QCC performing the set of quantum-logic stabilizers on the set of logical qubits.

Inventors

  • TAN, Bochen
  • GIDNEY, Craig
  • NIU, Yuezhen

Assignees

  • Google LLC

Dates

Publication Date
20260513
Application Date
20240809

Claims (20)

  1. WHAT IS CLAIMED IS: 1. A method for implementing fault-tolerant quantum computing, the method comprising: receiving a set of inputs for a fault-tolerant quantum-computation circuit (QCC), wherein the set of inputs includes an indication of a set of logical qubits and an indication of a set of quantum-logic stabilizers that the QCC is configured to perform on the set of logical qubits; generating a satisfiability modulo theory (SMT) model for the QCC based on the set of inputs, wherein the SMT model includes a set of constraints; and determining a set of values to populate a data structure, wherein the set of values satisfies the set of constraints of the SMT model, and the data structure populated by the set of values encodes an intermediate representation (IR) of a time evolution of the QCC performing the set of quantum-logic stabilizers on the set of logical qubits.
  2. 2. The method of claim 1, further comprising: in response to determining that the SMT model is satisfiable, receiving a set of additional constraints for the QCC; determining a reduced search space for the set of values based on the set of additional constraints; determining that the SMT model is satisfiable in accordance with the set of additional constraints based on the reduced search space for the set of values; in response to determining that the SMT model is satisfiable in accordance with the set of additional constraint, updating the set of values to populate the data structure based on the reduced search space; and generating the IR based on the updated set of values to populate the data structure.
  3. 3. The method of claim 1, wherein an SMT solver is employed to determine that the SMT model is satisfiable.
  4. 4. The method of claim 1, further comprising: generating a 3D model of time evolution of the QCC based on the IR; and generating a visual representation of a pipe diagram based on the 3D model, wherein the pipe diagram provides a visualization of the time evolution of the QCC.
  5. 5. The method of claim 1, wherein the set of inputs further includes a number of dimensions and the SMT model is based on the number of dimensions.
  6. 6. The method of claim 1, further comprising: generating a 3D model of time evolution of the QCC based on the IR, wherein the 3D model is encoded in a glTF file.
  7. 7. The method of claim 1, wherein each logical qubit of the set of logical qubits is encoded in a patch of surface code memory of a quantum computing system (QCS).
  8. 8. The method of claim 7, wherein the IR of the time evolution of the QCC encodes a pipe diagram of the time evolution of the QCC and the set of quantum-logic stabilizers includes lattice surgery operations on the set of logical qubits for the fault-tolerant quantum computing.
  9. 9. The method of claim 8, wherein each logical qubit of the set of logical qubits is represented by a cube in the pipe diagram and the pipe diagram includes a set of cubes representing the set of logical qubits and a set of interactions between the logical qubits of the set of qubits.
  10. 10. The method of claim 9, wherein at least a portion of the cubes in the set of cubes is elongated to generate a tube for the elongated tunes and the pipe diagram includes a set of tubes corresponding to the time evolution of the QCC and the set of interactions between the logical qubits of the set of qubits.
  11. 11. The method of claim 10, wherein a color of each edge of each tube of the set of tubes indicates a basis for a syndrome measurement corresponding to a boundary of the patch of surface code memory for the corresponding logical qubit.
  12. 12. The method of claim 11, wherein the set of constraints includes a requirement that colors of edges of tubes touching one another must match, indicating that basis for the syndrome measurements of boundaries of patches of the surface code memory being joined must be of a same basis type.
  13. 13. The method of claim 12, wherein the set of inputs includes a set of ports corresponding to the set of logical qubits, a set of structural variables, and a set of correlation surface variables.
  14. 14. The method of claim 13, wherein the set of structural variables specifies a structure of the pipe diagram, and a functionality of the pipe diagram is indicated by a set of stabilizers in the SMT model.
  15. 15. The method of claim 14, wherein determining that the SMT model is satisfiable includes determining that the SMT model implements the functionality of the pipe diagram via the set of stabilizers.
  16. 16. The method of claim 1, wherein the SMT model is a Boolean Satisfiability (SAT) model and the data structure includes a set of Boolean variables.
  17. 17. The method of claim 1, wherein determining the set of values to populate the data structure includes a SMT-based compilation of the QCC.
  18. 18. The method of claim 1, further comprising: generating a 3D model of the time evolution of the QCC based on the IR; and performing a simulation of the time evolution of the QCC based on the 3D model.
  19. 19. A computing system, comprising: one or more processor devices; one or more memory devices, the one or more memory devices storing computer- readable instructions that when executed by the one or more processor devices cause the one or more processor devices to perform operations for implementing fault-tolerant quantum computing, the operations comprising: receiving a set of inputs for a fault-tolerant quantum-computation circuit (QCC), wherein the set of inputs includes an indication of a set of logical qubits and an indication of a set of quantum-logic stabilizers that the QCC is configured to perform on the set of logical qubits; generating a satisfiability modulo theory (SMT) model for the QCC based on the set of inputs, wherein the SMT model includes a set of constraints; and determining a set of values to populate a data structure, wherein the set of values satisfies the set of constraints of the SMT model, and the data structure populated by the set of values encodes an intermediate representation (IR) of a time evolution of the QCC performing the set of quantum-logic stabilizers on the set of logical qubit.
  20. 20. The computing system of claim 19, wherein the operations further comprise: in response to determining that the SMT model is satisfiable, receiving a set of additional constraints for the QCC; determining a reduced search space for the set of values based on the set of additional constraints; determining that the SMT model is satisfiable in accordance with the set of additional constraints based on the reduced search space for the set of values; in response to determining that the SMT model is satisfiable in accordance with the set of additional constraint, updating the set of values to populate the data structure based on the reduced search space; and generating the IR based on the updated set of values to populate the data structure

Description

GENERATION AND COMPILATION OF REPRESENTATIONS OF FAULT TOLERANT QUANTUM CIRCUITS PRIORITY CLAIM [0001] This application claims priority to U.S. Provisional App. No.63/518,693 (Attorney Docket No. GGLQ-165-P) having a filing date of August 10, 2023, and entitled “GENERATION AND COMPILATION OF REPRESENTATIONS OF FAULT TOLERANT QUANTUM CIRCUITS,” the contents of which are herein incorporated in their entirety. FIELD [0002] The present disclosure relates generally to quantum computing and information processing systems, and more particularly to generating and compiling representations of fault-tolerant quantum circuits. BACKGROUND [0003] Quantum computing is a computing method that takes advantage of quantum effects, such as superposition of basis states and entanglement to perform certain computations more efficiently than a classical digital computer. In contrast to a digital computer, which stores and manipulates information in the form of bits, e.g., a “1” or “0,” quantum computing systems can manipulate information using quantum bits (“qubits”). A qubit can refer to a quantum device that enables the superposition of multiple states, e.g., data in both the “0” and “1” state, and/or to the superposition of data, itself, in the multiple states. In accordance with conventional terminology, the superposition of a “0” and “1” state in a quantum system may be represented, e.g., as a |0^ + b |1^ The “0” and “1” states of a digital computer are analogous to the |0^ and |1^ basis states, respectively of a qubit. SUMMARY [0004] Aspects and advantages of embodiments of the present disclosure will be set forth in part in the following description, or can be learned from the description, or can be learned through practice of the embodiments. [0005] One example aspect of the present disclosure is directed to a method for implementing fault-tolerant quantum computing. The method includes receiving a set of inputs for a fault-tolerant quantum-computation circuit (QCC). The set of inputs includes an indication of a set of logical qubits and an indication of a set of quantum-logic stabilizers that the QCC is configured to perform on the set of logical qubits. A satisfiability modulo theory (SMT) model for the QCC is generated based on the set of inputs. The SMT model includes a set of constraints. A set of values to populate a data structure. The set of values satisfies the set of constraints of the SMT model. The data structure populated by the set of values encodes an intermediate representation (IR) of a time evolution of the QCC performing the set of quantum-logic stabilizers on the set of logical qubits. [0006] Other aspects of the present disclosure are directed to various systems, methods, apparatuses, non-transitory computer-readable media, computer-readable instructions, and computing devices. [0007] These and other features, aspects, and advantages of various embodiments of the present disclosure will become better understood with reference to the following description and appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate example embodiments of the present disclosure and, together with the description, explain the related principles. BRIEF DESCRIPTION OF THE DRAWINGS [0008] Detailed discussion of embodiments directed to one of ordinary skill in the art is set forth in the specification, which refers to the appended figures, in which: [0009] FIG.1 depicts an example quantum computing system according to example embodiments of the present disclosure; [0010] FIG.2A illustrates “compact” pipe diagrams that show a CNOT operation on two logical qubits, according to various embodiments; [0011] FIG.2B illustrates “elongated” pipe diagrams that show the CNOT operation of FIG.2A, according to various embodiments; [0012] FIG.3 shows a lattice surgery operation, according to various embodiments; [0013] FIG.4 shows a ZX diagram and a corresponding pipe diagram, according to various embodiments; [0014] FIG.5A shows various pipe diagrams displaying visual manifestations of various structural variables, according to various embodiments; [0015] FIG.5B shows various pipe diagrams displaying visual manifestations of various correlational surface variables, according to various embodiments; [0016] FIG.6A shows various pipe diagrams displaying visual manifestations of various structural internal constraints, according to various embodiments; [0017] FIG.6B shows various pipe diagrams displaying visual manifestations of various stabilizer boundary constraints, according to various embodiments; [0018] FIG.7 shows a software structure 700 for a lattice surgery compiler, according to various embodiments; and [0019] FIG.8 depicts a flow chart diagram of an example method 800 for implementing fault-tolerant quantum computing, according to various embodiments. DETAILED DESCRIPTION [0020] Example aspects of the present disclosure are directed to methods, architectur