EP-4740239-A1 - BODY TIED TO SOURCE STANDARD CELL IMPLEMENTATIONS IN SEMICONDUCTOR-ON-INSULATOR (SOI) TECHNOLOGY

Abstract

An integrated circuit (IC) device is described. The IC device includes a semiconductor-on-insulator (SOI) substrate having a first-type diffusion region. The IC device also includes a first, first-type transistor on the first-type diffusion region. The IC device further includes a second, first-type transistor on the first-type diffusion region. The IC device also includes a first, second-type implant region. The first, second-type implant region includes a gate overlap region partially overlapped with a gate region of the second, first-type transistor to provide a body contact of the second, first-type transistor and to couple a source region of the second, first-type transistor to a drain region of the first, first-type transistor in series.

Inventors

• VEDULA, Ravi Pramod Kumar
• PAUL, ABHIJEET

Assignees

• QUALCOMM INCORPORATED

Dates

Publication Date

20260513

Application Date

20240809

Claims (20)

1. 1. An integrated circuit (IC) device, comprising: a semiconductor-on-insulator (SOI) substrate having a first-type diffusion region; a first, first-type transistor on the first-type diffusion region; a second, first-type transistor on the first-type diffusion region; and a first, second-type implant region, comprising a gate overlap region partially overlapped with a gate region of the second, first-type transistor to provide a body contact of the second, first-type transistor and to couple a source region of the second, first-type transistor to a drain region of the first, first-type transistor in series.
2. 2. The IC device of claim 1. further comprising a first, second-type transistor on a second-type diffusion region of the SOI substrate and having a gate region aligned with a gate region of the first, first-type transistor.
3. 3. The IC device of claim 2, in which the first, second-type transistor comprises an N-type metal oxide semiconductor (NMOS) transistor and the first, first- type transistor comprises a P-type metal oxide semiconductor (PMOS) transistor.
4. 4. The IC device of claim 2. in which the SOI substrate comprises a shallow trench isolation (STI) region between the first-type diffusion region and the second-type diffusion region.
5. 5. The IC device of claim 2. in which the first, second-type transistor comprises a first-type implant region, comprising a gate overlap region partially overlapped with the gate region of the first, second-type transistor to provide a body contact of the first, second-type transistor.
6. 6. The IC device of claim 2, further comprising a second, second-type transistor on the second-type diffusion region of the SOI substrate and having a gate region aligned with the gate region of the second, first-type transistor.
7. 7. The 1C device of claim 1. in which the first-type diffusion region comprises a P+ diffusion region.
8. 8. The IC device of claim 1, in which the second-type implant region comprises an N+ implant region.
9. 9. The IC device of claim 1. in which the IC device comprises a logic device.
10. 10. The IC device of claim 9, in which the logic device is integrated in at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.
11. 11. A method for constructing a poly-shadow implant body tied to source (BTS) integrated circuit (IC) device, the method comprising: forming a first-type diffusion region on a semiconductor-on-insulator (SOI) substrate; forming a first, first-type transistor on the first-type diffusion region; forming a second, first-ty pe transistor on the first-type diffusion region; and forming a first, second-type implant region, comprising a gate overlap region partially overlapped with a gate region of the second, first-ty pe transistor to provide a body contact of the second, first-type transistor and to couple a source region of the second, first-type transistor to a drain region of the first, first-type transistor in series.
12. 12. The method of claim 11, further comprising forming a first, second-type transistor on a second-type diffusion region of the SOI substrate and having a gate region aligned with a gate region of the first, first-type transistor.
13. 13. The method of claim 12, in which the first, second-type transistor comprises an N-type metal oxide semiconductor (NMOS) transistor and the first, first- type transistor comprises a P-type metal oxide semiconductor (PMOS) transistor.
14. 14. The method of claim 12, in which the SOI substrate comprises a shallow trench isolation (STI) region between the first-type diffusion region and the second-type diffusion region.
15. 15. The method of claim 12, in which the first, second-type transistor comprises a first-type implant region, comprising a gate overlap region partially overlapped with the gate region of the first, second-type transistor to provide a body contact of the first, second-type transistor.
16. 16. The method of claim 12, further comprising forming a second, second- type transistor on the second-type diffusion region of the SOI substrate and having a gate region aligned with the gate region of the second, first-type transistor.
17. 17. The method of claim 11, in which the first-tj pe diffusion region comprises a P+ diffusion region.
18. 18. The method of claim 11 , in which the second-type implant region comprises an N+ implant region.
19. 19. The method of claim 11, in which the poly-shadow implant BTS IC device comprises a logic device.
20. 20. The method of claim 19, further comprising integrating the logic device in at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

Description

BODY TIED TO SOURCE STANDARD CELL IMPLEMENTATIONS IN SEMICONDUCTOR-ON-INSULATOR (SOI) TECHNOLOGY CROSS-REFERENCE TO RELATED APPLICATION [0001] The present application claims priority to U.S. Patent Application No. 18/477,508, filed on September 28, 2023, and titled “BODY TIED TO SOURCE STANDARD CELL IMPLEMENTATIONS IN SEMICONDUCTOR-ON- INSULATOR (SOI) TECHNOLOGY,” the disclosure of which is expressly incorporated by reference in its entirety. TECHNICAL FIELD [0002] The present disclosure relates to integrated circuits (ICs). More specifically, the present disclosure relates to a body tied to source standard cell implementations in semiconductor-on-insulator (SOI) technology. BACKGROUND [0003] The design complexity of mobile integrated circuit (IC) s is complicated by added circuit functions for supporting communications enhancements. Designing mobile ICs may include using semiconductor-on-insulator (SOI) technology. SOI technology7 replaces conventional semiconductor (e.g., silicon) substrates with a layered semiconductor-insulator-semiconductor substrate for reducing parasitic device capacitance and improving performance. SOI-based devices differ from conventional, silicon-built devices because a silicon junction is above an electrical isolator, typically a buried oxide (BOX) layer. A reduced thickness BOX layer, however, may not sufficiently reduce artificial harmonics caused by the proximity of an active device on the SOI layer and an SOI substrate supporting the BOX layer. [0004] For example, high performance transistors are currently manufactured using SOI substrates. Additionally, traditional floating body transistors exhibit great radio frequency (RF)-SOI performance, but suffer from a floating body effect, in which the transistor body collects a charge generated at the junctions of the transistor device. As described, this floating body effect is referred to as a kink effect. IC performance is central and important to product development, while the kink effect impacts the switching speed and maximum frequency that can be supported. As communication protocols become increasingly stringent, there is a need for faster switching. This switching speed is limited by the inherent transistor device design process. Additionally, the switching delay cannot be completely fixed by design or software. SUMMARY [0005] An integrated circuit (IC) device is described. The IC device includes a semiconductor-on-insulator (SOI) substrate having a first-tj pe diffusion region. The TC device also includes a first, first-type transistor on the first-type diffusion region. The IC device further includes a second, first-type transistor on the first-type diffusion region. The IC device also includes a first, second-type implant region. The first, second-ty pe implant region includes a gate overlap region partially overlapped with a gate region of the second, first-type transistor to provide a body contact of the second, first-type transistor and to couple a source region of the second, first-type transistor to a drain region of the first, first-type transistor in series. [0006] A method for constructing a poly-shadow implant body tied to source (BTS) integrated circuit (IC) device is described. The method includes forming a first-type diffusion region on a semiconductor-on-insulator (SOI) substrate. The method also includes forming a first, first-type transistor on the first-type diffusion region. The method further includes forming a second, first-type transistor on the first-type diffusion region. The method also includes forming a first, second-type implant region. The first, second-type implant region includes a gate overlap region partially overlapped with a gate region of the second, first-type transistor to provide a body contact of the second, first-type transistor and to couple a source region of the second, first-type transistor to a drain region of the first, first-type transistor in series. [0007] This has outlined, broadly, the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the present disclosure will be described below. It should be appreciated by those skilled in the art that this present disclosure may be readily utilized as a basis for modifying or designing other structures for conducting the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features, which are believed to be characteristic of the present disclosure, both as to its organization and method of operation, together with further objects and advantages, will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figur