EP-4740244-A1 - INTEGRATED DEVICE COMPRISING METALLIZATION INTERCONNECTS

Abstract

An integrated device comprising a die substrate; a die interconnection portion coupled to the die substrate; and a metallization interconnect coupled to the die interconnection portion. The metallization interconnect comprises an adhesion metal layer; a first metal layer coupled to the adhesion metal layer; a second metal layer coupled to the first metal layer; and a third metal layer coupled to the second metal layer.

Inventors

• Yong, Poh Hoong
• Poh, Siew Li
• YANG, Ren Bin
• CHEN, SHAN

Assignees

• RF360 Singapore Pte. Ltd.

Dates

Publication Date

20260513

Application Date

20240621

Claims (20)

1. 1. An integrated device comprising: a die substrate; a die interconnection portion coupled to the die substrate; and a metallization interconnect coupled to the die interconnection portion, wherein the metallization interconnect comprises: an adhesion metal layer; a first metal layer coupled to the adhesion metal layer; a second metal layer coupled to the first metal layer; and a third metal layer coupled to the second metal layer.
2. 2. The integrated device of claim 1, further comprising a solder interconnect coupled to the metallization interconnect.
3. 3. The integrated device of claim 1, wherein the adhesion metal layer includes titanium (Ti).
4. 4. The integrated device of claim 1 , wherein the first metal layer includes aluminum (Al) and/or copper (Cu).
5. 5. The integrated device of claim 1, wherein the second metal layer includes copper (Cu) and/or nickel (Ni).
6. 6. The integrated device of claim 1, wherein the third metal layer includes gold (Au).
7. 7. The integrated device of claim 6, further comprising a solder interconnect coupled to the third metal layer of the metallization interconnect.
8. 8. The integrated device of claim 1, wherein the second metal layer is a wetting layer and/or a barrier layer, and wherein the third metal layer is a protection layer.
9. 9. The integrated device of claim 1, further comprising a passivation layer located over a portion of the metallization interconnect, wherein the passivation layer includes an opening through which a solder interconnect is coupled to the metallization interconnect, and wherein the passivation layer touches the adhesion metal layer, the first metal layer, the second metal layer and the third metal layer.
10. 10. The integrated device of claim 1, wherein the metallization interconnect includes an under bump metallization (UBM) interconnect.
11. 11. An integrated device comprising: a die substrate; and a metallization interconnect coupled to the die substrate, wherein the metallization interconnect comprises: an adhesion metal layer; a first metal layer coupled to the adhesion metal layer; a second metal layer coupled to the first metal layer; and a third metal layer coupled to the second metal layer.
12. 12. The integrated device of claim 11, further comprising a solder interconnect coupled to the metallization interconnect.
13. 13. The integrated device of claim 11, wherein the adhesion metal layer includes titanium (Ti).
14. 14. The integrated device of claim 1 1 , wherein the first metal layer includes aluminum (Al) and/or copper (Cu).
15. 15. The integrated device of claim 11, wherein the second metal layer includes copper (Cu) and/or nickel (Ni).
16. 16. The integrated device of claim 11, wherein the third metal layer includes gold (Au).
17. 17. The integrated device of claim 16, further comprising a solder interconnect coupled to the third metal layer of the metallization interconnect.
18. 18. The integrated device of claim 11, wherein the second metal layer is a wetting layer and/or a barrier layer, and wherein the third metal layer is a protection layer.
19. 19. The integrated device of claim 11, further comprising a passivation layer located over a portion of the metallization interconnect, wherein the passivation layer includes an opening through which a solder interconnect is coupled to the metallization interconnect, wherein the passivation layer touches the adhesion metal layer, the first metal layer, the second metal layer and the third metal layer, and wherein the metallization interconnect includes an under bump metallization (UBM) interconnect.
20. 20. The integrated device of claim 11, wherein the integrated device is implemented in a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (loT) device, and a device in an automotive vehicle.

Description

INTEGRATED DEVICE COMPRISING METALLIZATION INTERCONNECTS CROSS-REFERENCE TO RELATED APPLICATION [0001] This application claims priority to and the benefit of U.S. Non-Provisional Application Serial No. 18/346,701 filed in the United States Patent and Trademark Office on July 3, 2023, the entire content of which is incorporated herein by reference as if fully set forth below in its entirety and for all applicable purposes. Field [0002] Various features relate to integrated devices. Background [0003] A package may include a substrate and integrated devices. These components are coupled together to provide a package that may perform various functions. The performance of a package and its components may depend on how these components are configured together. Interconnects are an important part of an integrated device. There is an ongoing need to provide integrated devices with reliable interconnects and interconnects with low resistance, which can result in interconnects with improved electrical conductivity. SUMMARY [0004] Various features relate to integrated devices [0005] One example provides an integrated device comprising a die substrate; a die interconnection portion coupled to the die substrate; and a metallization interconnect coupled to the die interconnection portion. The metallization interconnect comprises an adhesion metal layer; a first metal layer coupled to the adhesion metal layer; a second metal layer coupled to the first metal layer; and a third metal layer coupled to the second metal layer. [0006] One example provides an integrated device comprising a die substrate; and a metallization interconnect coupled to the die substrate. The metallization interconnect comprises an adhesion metal layer; a first metal layer coupled to the adhesion metal layer; a second metal layer coupled to the first metal layer; and a third metal layer coupled to the second metal layer. [0007] Another example provides a method for fabricating an integrated device. The method provides a die substrate. The method forms a metallization interconnect. The metallization interconnect comprises an adhesion metal layer; a first metal layer coupled to the adhesion metal layer; a second metal layer coupled to the first metal layer; and a third metal layer coupled to the second metal layer. BRIEF DESCRIPTION OF THE DRAWINGS |0008| Various features, nature and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout. [0009] FIG. 1 illustrates a profile cross sectional view of an exemplary integrated device. [0010] FIG. 2 illustrates a close-up profile cross sectional view of an exemplary integrated device. [0011] FIG. 3 illustrates a profile cross sectional view of another exemplary integrated device. [0012] FIG. 4 illustrates a close-up profile cross sectional view of another exemplary integrated device. [0013] FIGS. 5A-5F illustrate an exemplary sequence for fabricating an integrated device. [0014] FIG. 6 illustrates an exemplary flow diagram of a method for fabricating an integrated device. [0015] FIGS. 7A-7B illustrate an exemplary sequence for fabricating another integrated device. [0016] FIG. 8 illustrate an exemplary sequence for fabricating another integrated device. [0017] FIG. 9 illustrates an exemplary flow diagram of a method for fabricating an integrated device. [0018] FIG. 10 illustrates various electronic devices that may integrate a die, an electronic circuit, an integrated device, an integrated passive device (IPD), a passive component, a package, and/or a device package described herein. DETAILED DESCRIPTION [0019] In the following description, specific details are given to provide a thorough understanding of the various aspects of the disclosure. However, it will be understood by one of ordinary skill in the art that the aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams in order to avoid obscuring the aspects in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure the aspects of the disclosure. [0020] The present disclosure describes an integrated device comprising a die substrate; a die interconnection portion coupled to the die substrate; and a metallization interconnect coupled to the die interconnection portion. The metallization interconnect comprises an adhesion metal layer; a first metal layer coupled to the adhesion metal layer; a second metal layer coupled to the first metal layer; and a third metal layer coupled to the second metal layer. The die interconnection portion may be optional. The metallization interconnect may represent a metallization interconnect and an under bump metallization interconnect. As will be further described below, the metallization interconnect may be fabricated using less metal layers and less s