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EP-4740277-A1 - PHOTONIC CHIP HAVING A HETEROGENEOUS III-V SEMICONDUCTOR STRUCTURE ON A SECOND SEMICONDUCTOR

EP4740277A1EP 4740277 A1EP4740277 A1EP 4740277A1EP-4740277-A1

Abstract

The invention relates to a photonic chip (10) having a heterogeneous III-V semiconductor structure on a second semiconductor comprising, in a stacking direction (Δ): a waveguide (11) made of a first III-V semiconductor material, referred to as the lll-V waveguide, comprising a first confinement layer (110), an active layer (111) and a second confinement layer (112), a waveguide (12) made of a second semiconductor material, referred to as the SC waveguide, comprising a layer (120) of the second semiconductor material. The first confinement layer (110) comprising a first portion (110a) on top of the active layer (111) and at least one extension (110b) extending laterally beyond the active layer (111), the extension (110b) having a thickness (Eb) in the stacking direction that is greater than that (Ea) of the first portion (110a) so as to define an electrical contact face (116) located before the first portion (110a) in the stacking direction (Δ).

Inventors

  • RAMIREZ, Joan
  • BESANCON, Claire

Assignees

  • THALES
  • Commissariat à l'Energie Atomique et aux Energies Alternatives

Dates

Publication Date
20260513
Application Date
20240705

Claims (10)

  1. 1. Photonic chip (10,20,30) with a heterogeneous structure of III-V semiconductor on a second semiconductor comprising, in a stacking direction (A): i. a waveguide (11) made of a first III-V semiconductor material, called III-V waveguide, comprising a first confinement layer (110), an active layer (111) and a second confinement layer (112), ii. a waveguide (12) made of a second semiconductor material, called an SC waveguide, comprising a layer (120) of the second semiconductor material, the III-V waveguide (11) further comprising a first electrode (B1) and a second electrode (B2) configured to respectively ensure electrical contact with one of said confinement layers, such that the active layer (111) emits a light wave when an electric current (i) flows between said electrodes through the active layer (111) and the confinement layers, the first confinement layer (110) comprising a first portion (110a) superimposed on the active layer (111) and at least one extension (110b), extending laterally beyond said active layer (111), said extension (110b) having a thickness (Eb) in the stacking direction (A) which is greater than that (Ea) of the first portion (110a), so as to define an electrical contact face (116) located before the first portion (110a) along the stacking direction (A), said first electrode (B1) comprising a first contact layer (B10) coming against said electrical contact face (116).
  2. 2. Photonic chip (10, 20, 30) according to claim 1, in which the thickness (Eb) of the extension (110b) defines at least one staircase-shaped portion comprising a low landing separated from a high landing by a step height, the low landing comprising an external face (117) of the first portion (110a) of the first confinement layer (110), the high landing comprising the contact face (116) of the first confinement layer (110), the distance between the foot of the step height and the first portion (110a) being between 0 and 2 pm.
  3. 3. Photonic chip (10, 20, 30) according to the preceding claim, in which the distance between the foot of the step height and the first portion (110a) of the first confinement layer (110) is equal to zero.
  4. 4. Photonic chip (10, 20, 30) according to one of the preceding claims, wherein the thickness (Eb) of the extension (110b) is configured to avoid an intervalence band absorption phenomenon in the III-V waveguide (11); and the first portion (110a) has a thickness (Ea) configured for a phase matching condition between the III-V waveguide (11) and the SC waveguide (12).
  5. 5. Photonic chip (10, 20, 30) according to one of the preceding claims, in which the extension (110b) has a doping profile decreasing from the contact face (116) along said stacking direction (A); and the first portion (110a) of the first confinement layer (110) has a substantially constant doping.
  6. 6. Photonic chip (10, 20, 30) according to one of the preceding claims, in which the waveguides (11, 12) extend in a longitudinal direction, said chip comprising a transition zone (17) in which the III-V waveguide (11) and/or the SC waveguide (12) have a profiling along said longitudinal direction making it possible to transmit an optical mode between the III-V waveguide (11) and the SC waveguide (12).
  7. 7. Photonic chip (10, 20, 30) according to the preceding claim, in which said extension (110b) is at least included in said transition zone (17).
  8. 8. Photonic chip (20) according to claim 6 or 7, wherein, outside said transition zone (17), the first confinement layer (110) consists of the first portion (110a) and has a thickness (Ea) configured to avoid an intervalence band absorption phenomenon in the III-V waveguide (11).
  9. 9. Photonic chip (10, 20, 30) according to one of the preceding claims, in which the second confinement layer (112) extends at least partly laterally beyond the active layer (111) and the first confinement layer (110); and the second electrode (B2) comprises at least one via extending along the stacking direction (A), in particular on the side of the first confinement layer (110) and the active layer (111).
  10. 10. Photonic chip (30) according to one of the preceding claims, in which said first confinement layer (110) comprises two extensions (310b) each extending from opposite edges of said first portion (110a) of the first confinement layer (110).

Description

DESCRIPTION Title of the invention: Photonic chip with heterogeneous structure of III-V semiconductor on a second semiconductor [0001] The invention relates to a photonic chip with a heterogeneous structure of III-V semiconductor on a second semiconductor allowing efficient transmission, in particular adiabatic, without loss, of an optical mode between a waveguide made of a first III-V semiconductor material and a waveguide made of a second semiconductor material. [0002] There is interest in photonic circuits integrated on silicon chips using silicon optical guides. Such photonic circuits have the advantage of being achievable with the large-scale manufacturing lines of well-known CMOS technologies. However, silicon is a semiconductor that is poorly suited for use as a laser source or optical amplifier, due to some of its physical parameters, in particular its indirect gap. [0003] However, III-V semiconductor structures are known for the production of efficient optical sources. Heterogeneous structures are therefore developed which integrate III-V type semiconductors on silicon wafers. These heterogeneous structures therefore combine the versatility, high density, and scalability of CMOS technology with the optical gain of III-V semiconductor materials. [0004] Figure 1 illustrates an example of a heterogeneous structure 50 according to the prior art. The structure 50 comprises a first waveguide 51 made of III-V semiconductor material coupled to a second waveguide 52 made of silicon material. The III-V waveguide 51 comprises a first p-doped confinement layer 510 and a second n-doped confinement layer 512, on either side of an active layer 511 containing multiple quantum wells (or MQWs for “Multi Quantum Wells” in English). The first p-doped confinement layer 510 comprises on its external face a highly p-doped layer 508 so as to improve electrical contact with an electrode layer 506. Electrodes 534, 536 allow an electrical connection of the second n-doped confinement layer 512, in particular at a highly n-doped zone of the second n-doped confinement layer. The second optical guide 52 comprises a silicon layer 520. The guides 51, 52 are separated by a material 55 made of silicon oxide SiO2 and are sufficiently close to allow optical coupling between them. [0005] Typically, III-V quantum well structures are susceptible to the phenomenon of interval band absorption (or IVBA) in which the light signal interacts with the p-doping of the first p-doped confinement layer. This results in optical losses that degrade laser performance. To minimize this effect, the first p-doped confinement layer 510 is relatively thicker than the second n-doped confinement layer 512 in order to distance the heavily p-doped layer 508 from the active layer 511. The first confinement layer 510 may further have a doping gradient from the heavily doped layer 508 to the active layer 511 to further attenuate the IVBA phenomenon. The optical signal produced by the quantum wells of the active layer 511 then interacts mainly with the lightly p-doped areas of the first confinement layer 510, which allows for low or moderate absorption. [0006] Now, for an efficient optical mode transfer between the III-V waveguide 51 and the silicon waveguide 52, a phase matching condition must be respected. For this purpose, the III-V waveguide 51 and the silicon waveguide 52 must have equal effective propagation indices in the area, called the transition area, where the optical mode transfer must occur. The effective propagation index n e ff is also known as the "mode phase constant". It is defined by the following relationship: [Math 1] where n g is the group index and A is the wavelength of the optical signal guided by the waveguide. The effective propagation index of a waveguide depends on the dimensions of the core of this waveguide and the indices of the materials forming the core and the cladding of this waveguide. It can be determined experimentally or by numerical simulation. [0007] Photonic chips can be fabricated from a silicon-on-oxide (SOI) substrate. The thickness of the layer in monocrystalline silicon of such an SOI substrate is typically between 220 and 300 nm. In the structure of FIG. 1 , the III-V waveguide 51 generally has a thickness between 2 and 3 pm. Such a thickness of the III-V waveguide 51 does not allow a phase matching condition to be obtained with a silicon waveguide with a thickness between 220 and 300 nm. The optical mode transmission between the III-V waveguide and the silicon waveguide could then not be done without losses. To overcome this, in FIG. 1 , the thickness of the silicon layer of the silicon guide 52 is increased compared to the conventional thickness, to reach an E2 value between 400 and 500 nm. In the heterogeneous structure 50 illustrated in FIG. 1 , the silicon layer has in particular a thickness E2 of 500 nm which makes it possible to obtain a phase matching condition between the guides 51 , 52. However, having