EP-4740303-A1 - SUPERCONDUCTING PASSIVE TRANSMISSION LINE (PTL) RECEIVER SYSTEM

Abstract

One example includes a PTL receiver system. The system includes a receiver core that comprises an input Josephson junction and that receives an input pulse from a PTL. The system also includes an active bias circuit which generates a bias pulse based on a bias clock signal and provides the bias pulse to the receiver core. The bias pulse can have a pulse-width approximately one-half a period of the bias clock signal. The input Josephson junction can trigger to generate an intermediate pulse in response to the input and bias pulses. The system further includes an alignment JTL comprising at least one alignment Josephson junction. The alignment Josephson junction can be configured to trigger to generate an output pulse in response to the intermediate pulse and the bias clock signal to provide for reception of the input pulse across a wide timing window based on the bias pulse.

Inventors

• GEORGANTAS, Domenic Nickolas

Assignees

• Northrop Grumman Systems Corporation

Dates

Publication Date

20260513

Application Date

20240604

Claims (20)

1. 1. A passive transmission line (PTL) receiver system comprising: a receiver core comprising at least one input Josephson junction and configured to receive an input pulse from a PTL; an active bias circuit configured to generate a bias pulse based on a bias clock signal and to provide the bias pulse to the receiver core, the bias pulse having a bias amplitude pulse-width that is approximately one-half a period of the bias clock signal, the at least one input Josephson junction of the receiver core being configured to trigger to generate an intermediate pulse in response to the input pulse and the bias pulse; and an alignment Josephson transmission line (JTL) comprising at least one alignment Josephson junction, the at least one alignment Josephson junction of the alignment JTL being configured to trigger to generate an output pulse in response to the intermediate pulse and the bias clock signal to provide for reception of the input pulse across a wide timing window based on the bias pulse.
2. 2. The system of claim 1, wherein the active bias circuit comprises: a pulse generator configured to generate the bias pulse based on the bias clock signal; and a biasing buffer configured to amplify the bias pulse and to propagate the bias pulse to the receiver core.
3. 3. The system of claim 2, wherein the pulse generator comprises: a transformer comprising a primary configured to conduct a DC bias current and a secondary configured to provide an induced bias current based on the DC bias current; and a JTL coupled to the secondary and comprising a pulse generator Josephson junction, the pulse generator Josephson junction being biased by the induced bias current to trigger in response to an approximate positive zero-crossing of the bias clock signal.
4. 4. The system of claim 2, wherein the pulse generator is configured to generate the bias pulse based on a first phase of the bias clock signal, wherein the biasing buffer comprises at least one buffer JTL each comprising a buffer Josephson junction, wherein the buffer Josephson junction of each of the at least one buffer JTL triggers sequentially in response to respective phases of the bias clock signal subsequent to the first phase to propagate the bias pulse to the receiver core.
5. 5. The system of claim 4, wherein the buffer Josephson junction of a last one of the at least one buffer JTL has a critical current that is selected to be greater than a critical current associated with the at least one input Josephson junction to mitigate propagation of the intermediate pulse to the biasing buffer.
6. 6. The system of claim 1 , wherein the active bias circuit is configured to generate the bias pulse based on a first phase of the bias clock signal, wherein the alignment JTL is configured to trigger the at least one alignment Josephson junction to generate the output pulse in response to the intermediate pulse and a second phase of the bias clock signal subsequent to the first phase of the bias clock signal.
7. 7. The system of claim 6, wherein the second phase of the bias clock signal is less than or equal to approximately 90° subsequent to the first phase of the bias clock signal to provide pulse waiting for the input pulse based on a combination of the receiver core and the alignment JTL.
8. 8. The system of claim 1 , wherein the at least one input Josephson junction of the receiver core is selected to have a smaller biasing margin than the at least one alignment Josephson junction of the alignment JTL, wherein the active bias circuit is configured to regulate a peak amplitude of the bias pulse to be smaller than a peak amplitude of the bias clock signal.
9. 9. The system of claim 1 , wherein the active bias circuit is arranged as a phase-potential divider to provide sufficient bias of the at least one input Josephson junction to trigger the at least one input Josephson junction in response to the input pulse across the bias amplitude pulsewidth of approximately one -half the period of the bias clock signal.
10. 10. The system of claim 1, wherein the receiver core comprises an input resistor through which the input pulse is provided as a reciprocal quantum logic (RQL) pulse.
11. 11. A method for aligning a reciprocal quantum logic (RQL) input pulse from a passive transmission line (PTL) to a phase of a bias clock signal, the method comprising: providing a DC bias current to a primary of a transformer of an active bias circuit to provide an induced bias current on a secondary' of the transformer based on the DC bias current, the induced bias current providing a bias for a pulse-generator Josephson junction; providing the bias clock signal to the active bias circuit to trigger the pulse-generator Josephson junction in response to an approximate positive zero-crossing of a first phase of the bias clock signal to generate a bias pulse having a bias amplitude pulse-width that is approximately one-half a period of the bias clock signal; providing the RQL input pulse to a receiver core, the receiver core comprising at least one input Josephson junction configured to trigger in response to the RQL input pulse and to generate an intermediate pulse in response to RQL input pulse and the bias pulse; and providing the bias clock signal to an alignment Josephson transmission line (JTL) to trigger at least one alignment Josephson junction to generate an output pulse in response to the intermediate pulse and a second phase of the bias clock signal subsequent to the first phase to provide for reception of the input pulse across a wide timing window based on the bias pulse.
12. 12. The method of claim 11 , further comprising providing the bias clock signal at at least one third phase to a biasing buffer to amplifying the bias pulse and propagate the bias pulse to the receiver core, the at least one third phase of the bias clock signal being subsequent to the first phase and previous to or concurrent with the second phase.
13. 13. The method of claim 11 , wherein the second phase of the bias clock signal is less than or equal to approximately 90° subsequent to the first phase of the bias clock signal to provide pulse waiting for the RQL input pulse based on a combination of the receiver core and the alignment JTL.
14. 14. The method of claim 11, wherein providing the bias clock signal to the active bias circuit comprises providing the bias clock signal to the active bias circuit to trigger the pulse -generator Josephson junction in response to an approximate positive zero-crossing of the first phase of the bias clock signal to generate the bias pulse as a broad plateau pulse that is a combination of a sinusoidal wave and a square wave.
15. 15. The method of claim 11, wherein providing the bias clock signal to the active bias circuit comprises providing the bias clock signal to the active bias circuit to trigger the pulse-generator Josephson junction in response to an approximate positive zero-crossing of the first phase of the bias clock signal to generate the bias pulse as having sufficient bias of the at least one input Josephson junction to trigger the at least one input Josephson junction in response to the RQL input pulse across the bias amplitude pulse- width of approximately one-half the period of the bias clock signal.
16. 16. A reciprocal quantum logic (RQL) passive transmission line (PTL) receiver system comprising: a receiver core comprising an input resistor and at least one input Josephson junction and configured to receive a reciprocal quantum logic (RQL) input pulse from a PTL through the input resistor; an active bias circuit comprising: a pulse generator configured to generate a bias pulse based on a first phase of a bias clock signal, the bias pulse having a bias amplitude pulse-width that is approximately one-half a period of the bias clock signal; and a biasing buffer configured to amplify the bias pulse and to propagate the bias pulse to the receiver core, the at least one input Josephson junction of the receiver core being configured to trigger to generate an intermediate pulse in response to the RQL input pulse and the bias pulse; and an alignment Josephson transmission line (JTL) comprising at least one alignment Josephson junction, the at least one alignment Josephson junction of the alignment JTL being configured to trigger to generate an output pulse in response to the intermediate pulse and a second phase of the bias clock signal that is subsequent to the first phase to provide for reception of the input pulse across a wide timing window based on the bias pulse.
17. 17. The system of claim 16, wherein the pulse generator comprises: a transformer comprising a primary configured to conduct a DC bias current and a secondary configured to provide an induced bias current based on the DC bias current; and a JTL coupled to the secondary and comprising a pulse generator Josephson junction, the pulse generator Josephson junction being biased by the induced bias current to trigger in response to an approximate positive zero-crossing of the bias clock signal.
18. 18. The system of claim 16, wherein the pulse generator is configured to generate the bias pulse based on the first phase of the bias clock signal, wherein the biasing buffer comprises at least one buffer JTL each comprising a buffer Josephson junction, wherein the buffer Josephson junction of each of the at least one buffer JTL triggers sequentially in response to respective phases of the bias clock signal subsequent to the first phase to propagate the bias pulse to the receiver core.
19. 19. The system of claim 18, wherein the buffer Josephson junction of a last one of the at least one buffer JTL has a critical current that is selected to be greater than a critical current associated with the at least one input Josephson junction to mitigate propagation of the intermediate pulse to the biasing buffer.
20. 20. The system of claim 16, wherein the al least one input Josephson junction of the receiver core is selected to have a smaller biasing margin than the at least one alignment Josephson junction of the alignment JTL, wherein the active bias circuit is configured to regulate a peak amplitude of the bias pulse to be smaller than a peak amplitude of the bias clock signal.

Description

SUPERCONDUCTING PASSIVE TRANSMISSION LINE (PTL) RECEIVER SYSTEM RELATED APPLICATIONS [0001] This application claims priority from U.S. Patent Application Serial No. 18/347884, filed 06 July 2023, which is incorporated herein in its entirety. GOVERNMENT INTEREST [0002] The invention was made under Government Contract. Therefore, the US Government has rights to the invention as specified in that contract. TECHNICAL FIELD [0003] The present invention relates generally to computer systems, and specifically to a superconducting PTL receiver system. BACKGROUND [0004] Superconducting digital technology has provided computing and/or communications resources that benefit from unprecedented high speed, low power dissipation, and low operating temperature. Superconducting digital technology has been developed as an alternative to CMOS technology, and typically comprises superconductor based single flux superconducting circuitry, utilizing superconducting Josephson junctions, and can exhibit typical signal power dissipation of less than 1 nW (nanowatt) per active device at a typical data rate of 20 Gb/s (gigabytes/second) or greater, and can operate at temperatures of around 4 Kelvin. [0005] Multiple Josephson junctions and inductors can be provided in a specific arrangement to provide a Josephson transmission line (JTL) to propagate data signals in superconductor computing systems, such as in a Reciprocal Quantum Logic (RQL) encoding scheme. As an example, the sequential triggering can be based on a bias current provided to a given one of the Josephson junctions, such that the Josephson junction is triggered in response to receiving the fluxon. As a result, the bias current can provided at a time that is approximately concurrent with or slightly after the arrival of the fluxon to provide appropriate timing for the triggering of the Josephson junction. By contrast, a passive transmission line (PTL) is not biased by a clock signal, and an associated PTL receiver cannot receive a fluxon prior to a bias current based on the presence of an input resistor. Therefore, it may therefore be difficult to align a fluxon arriving from a PTL to a specific phase of the clock signal at an associated PTL receiver. SUMMARY [0006] One example includes a superconducting PTL receiver system. The system includes a receiver core that comprises an input Josephson junction and that receives an input pulse from a PTL. The system also includes an active bias circuit which generates a bias pulse based on a bias clock signal and provides the bias pulse to the receiver core. The bias pulse can have a pulse-width approximately one -half a period of the bias clock signal. The input Josephson junction can trigger to generate an intermediate pulse in response to the input and bias pulses. The system further includes an alignment JTL comprising at least one alignment Josephson junction. The alignment Josephson junction can be configured to trigger to generate an output pulse in response to the intermediate pulse and the bias clock signal to provide for reception of the input pulse across a wide timing window based on the bias pulse. [0007] Another example includes a method for aligning a reciprocal quantum logic (RQL) input pulse from a passive transmission line (PTL) to a phase of a bias clock signal. The method includes providing a DC bias current to a primary of a transformer of an active bias circuit to provide an induced bias current on a secondary of the transformer based on the DC bias current. The induced bias current providing a bias for a pulse-generator Josephson junction. The method also includes providing the bias clock signal to the active bias circuit to trigger the pulsegenerator Josephson junction in response to an approximate positive zero-crossing of a first phase of the bias clock signal to generate a bias pulse having a bias amplitude pulse- width that is approximately one-half a period of the bias clock signal. The method also includes providing the RQL input pulse to a receiver core, the receiver core comprising at least one input Josephson junction configured to trigger in response to the RQL input pulse and the to generate an intermediate pulse in response to the input pulse and the bias pulse. The method further includes providing the bias clock signal to an alignment Josephson transmission line (JTL) to trigger at least one alignment Josephson junction to generate an output pulse in response to the intermediate pulse and a second phase of the bias clock signal subsequent to the first phase to provide for reception of the input pulse across a wide timing window based on the bias pulse. [0008] Another example includes a superconducting reciprocal quantum logic (RQL) passive transmission line (PTL) receiver system. The system includes a receiver core comprising an input resistor and at least one input Josephson junction and configured to receive a reciprocal quantum logic (RQL) input pulse from a PTL through the input resist