Search

EP-4740710-A2 - METHOD FOR FORMING A SEMICONDUCTOR DEVICE, AND A STRUCTURE FORMED BY THE METHOD

EP4740710A2EP 4740710 A2EP4740710 A2EP 4740710A2EP-4740710-A2

Abstract

A method for assembling a chip includes attaching a first side of each die of multiple dies to a respective at least one paddle of multiple paddles of a lead-frame strip, and attaching each of at least one paddle of multiple paddles of a clip-frame strip to a second side of the respective die of the multiple dies. As compared to a semiconductor-packaging method that places individual clips on the second sides of multiple dies one at a time, such a method can be less expensive, less complex, faster, have a higher yield, and/or can reduce the per-component cost of integrated circuits (ICs) and/or other components packaged according to this method.

Inventors

  • LIN, BARRY
  • CHIU, TONY

Assignees

  • Siliconix Incorporated

Dates

Publication Date
20260513
Application Date
20240802

Claims (20)

  1. 1. A method, comprising: attaching a first side of each die of multiple dies to a respective at least one paddle of multiple paddles of a lead-frame strip; and attaching each of at least one paddle of multiple paddles of a clip-frame strip to a second side of a respective said die of the multiple dies.
  2. 2. The method of claim 1 , wherein the attaching the first side includes attaching the first side of each said die of the multiple dies to the respective at least one paddle of the multiple paddles of the lead-frame strip one at a time.
  3. 3. The method of claim 1 , wherein the attaching each said at least one paddle of the multiple paddles includes attaching each of said at least one paddle of the multiple paddles of the clip-frame strip to the second side of the respective die of the multiple dies while the multiple paddles are connected to the clip-frame strip.
  4. 4. The method of claim 1 , wherein: the attaching the first side includes soldering the first side of each said die of the multiple dies to the respective at least one paddle of the multiple paddles of the lead-frame strip; and the attaching of each said at least one paddle of the multiple paddles of the clip-frame strip includes soldering each said at least one paddle of the multiple paddles of the clip-frame strip to the second side of the respective die of the multiple dies.
  5. 5. The method of claim 1 , further comprising: forming solder on each said at least one paddle of the multiple paddles of the lead-frame strip before attaching the first side of each said die of the multiple dies to the respective at least one paddle of the multiple paddles of the lead-frame strip; and forming solder on each said at least one paddle of the multiple paddles of the clip-frame strip before attaching each said at least one paddle of the multiple paddles of the clip-frame strip to the second side of the respective die of the multiple dies.
  6. 6. The method of claim 1 , further comprising aligning the clip-frame strip with the lead-frame strip before attaching each said at least one paddle of the multiple paddles of the clip-frame strip to the respective second side of each said die of the multiple dies.
  7. 7. The method of claim 1 , further comprising aligning alignment marks of the clip-frame strip with corresponding alignment marks of the lead-frame strip before attaching the multiple paddles of the clip-frame strip to the second sides of the multiple dies.
  8. 8. The method of claim 1 , further comprising encapsulating each said die of the multiple dies to form chips.
  9. 9. The method of claim 8, further comprising testing the chips before separating the chips from the lead-frame and the clip-frame strips.
  10. 10. The method of claim 8, further comprising de-junking the chips, the lead-frame strip, and the clip-frame strip before separating the chips from the lead-frame and the clip-frame strips.
  11. 11. The method of claim 8, further comprising plating exposed leads of the chips before separating the chips from the lead-frame and the clip-frame strips.
  12. 12. The method of claim 8, further comprising marking housings formed by the encapsulating of the chips before separating the chips from the lead-frame and clip-frame strips.
  13. 13. The method of claim 8, further comprising separating the chips from the lead-frame and the clip-frame strips.
  14. 14. The method of claim 13, further comprising shaping exposed leads of the chips after separating the chips from the lead-frame and the clip-frame strips.
  15. 15. The method of claim 1 , wherein: the lead frame includes at least one lead-frame block; a chip-frame including at least one chip-frame block; and the attaching each said at least one paddle of the multiple paddles of the clip-frame strip to the second side of the respective die of the multiple dies includes placing the at least one chipframe block over the at least one lead-frame block.
  16. 16. The method of claim 1 , wherein: the lead frame includes at least one lead-frame block; a chip-frame including at least one chip-frame block; and the attaching each said at least one paddle of the multiple paddles of the clip-frame strip to the second side of the respective die of the multiple dies includes placing the at least one chip- frame block over the at least one lead-frame block and aligning the at least one chip-frame block with the at least one lead-frame block.
  17. 17. A semiconductor structure, comprising: a lead frame having lead-frame paddles; a chip-frame having chip-frame paddles; dies each having a respective first side coupled to a respective lead-frame paddle of the lead-frame paddles and having a respective second side coupled to a respective chip-frame paddle of the chip-frame paddles.
  18. 18. The semiconductor structure of claim 17, further comprising: wherein each die of the multiple dies has a respective bond pad; wherein the lead frame or the chip-frame has multiple leads each corresponding to the respective die of the multiple dies; and bond wires each coupled between the bond pad of the respective die of the multiple dies and the corresponding lead of the multiple leads.
  19. 19. The semiconductor structure of claim 17, wherein: each said die of the multiple dies has a respective bond pad; the lead frame or the chip-frame has multiple leads each corresponding to the respective die of the multiple dies; and the other of the lead frame or the chip-frame has multiple extensions each coupled between the bond pad of the respective die of the multiple dies and the corresponding lead of the multiple leads.
  20. 20. The semiconductor structure of claim 17, wherein: each said die of the multiple dies has a respective bond pad; the lead frame has multiple leads each corresponding to the respective die of the multiple dies; and a clip-frame has multiple clip extensions each coupled between the bond pad of the respective die of the multiple dies and the corresponding lead of the multiple leads.

Description

METHOD FOR FORMING A SEMICONDUCTOR DEVICE, AND A STRUCTURE FORMED BY THE METHOD TECHNICAL FIELD [0001] The disclosure relates to a method for manufacturing (also called “fabricating”) semiconductor integrated circuits, and more specifically to an improved method for packaging semiconductor integrated circuits. BACKGROUND [0002] In the manufacture of known semiconductor integrated circuits, leads may be attached to both surfaces of a die. The attachment of one or more first leads to the die’s conductive pads on a first (bottom) surface can be accomplished by placing the die on a paddle of a lead frame and forming a conductive connection to the one or more first leads, for example by soldering. This can be done with multiple leads per die or dies simultaneously, prior to the leads/die(s) being separated from the lead frame. Connection of one or second leads to the conductive pad on a second (top) surface of the die is then carried out individually (/.e., typically not at the same time as other second leads are placed and attached) and in a more complex manner as compared to the placing and attaching of the one or more first leads. [0003] An improvement in this type of fabrication is needed to improve manufacturability as well as reduce the chance of defects. SUMMARY [0004] In an embodiment, a method is provided that includes attaching a first side of each die of multiple dies to a respective at least one paddle of multiple paddles of a lead-frame strip, and attaching each of at least one paddle of multiple paddles of a clip-frame strip to a second side of a respective die of the multiple dies. As compared to a semiconductor-packaging method that places individual clips on the second sides of multiple dies one at a time, such a method can be less expensive, less complex, and/or faster, can have a higher yield, and/or can reduce the per- component cost of integrated circuits (ICs) and/or other components packaged according to this method. [0005] In another embodiment, a semiconductor structure is provided that includes a lead frame having lead-frame paddles, a chip-frame having chip-frame paddles, and dies each having a respective first side coupled to a respective at least one lead-frame paddle of the lead-frame paddles and having a respective second side coupled to a respective at least one chip-frame paddle of the chip-frame paddles. BRIEF DESCRIPTION OF THE DRAWINGS [0006] A more detailed understanding may be had from the following description, given by way of example in conjunction with the accompanying drawings, wherein like reference numerals in the figures indicate like elements, and wherein: [0007] FIGS. 1A - 1B are lead-side and non-lead-side views, respectively, of an NMOS power transistor, according to an embodiment; [0008] FIG. 1C is a schematic symbol of the NMOS power transistor of FIGS. 1A - 1 B; [0009] FIGS. 2A - 2B are lead-side and non-lead-side views, respectively, of an NMOS power transistor represented by the schematic symbol of FIG. 1 C, according to another embodiment; [0010] FIG. 3A is plan view of a lead-frame (LF) strip and a chip-frame (CF) strip, according to an embodiment; [0011] FIG. 3B is a plan view of a CF block of the CF strip of FIG. 3A disposed over, and in alignment with, an LF block of the LF strip of FIG. 3A, according to an embodiment; [0012] FIG. 4 is a plan view of an LF block of an LF strip, according to an embodiment; [0013] FIGS. 5A - 5B are respective plan views of a bond-wireless version of the LF block of FIG. 4 with solder formed over the surfaces of the die paddles and lead bond pads, and of a bond-wire- reduced version of the LF block of FIG. 4 with solder formed over the surfaces of the die paddles and lead bond pads, according to an embodiment; [0014] FIGS. 6A - 6B are respective plan views of the bond-wireless version of the LF block of FIG. 5A with dies disposed over the pre-soldered die paddles, and of the bond-wire-reduced version of the LF strip of FIG. 5B with dies disposed over the pre-soldered die paddles, according to an embodiment; [0015] FIGS. 7A - 7B are respective plan views of the bond-wireless version of the LF block of FIG. 6A with solder formed over the exposed surfaces of the dies, and the bond-wire-reduced version of the LF block of FIG. 6B with solder formed over the exposed surfaces of the dies, according to an embodiment; [0016] FIG. 8A is a plan view of a CF block aligned with, and disposed over, the bond-wireless version of the LF block of FIG. 7A, and paddles of the CF block each disposed over an exposed surface of a respective die, according to an embodiment; [0017] FIG. 8B is a plan view of a CF block aligned with, and disposed over, the bond-wire- reduced version of the LF block of FIG. 7B, and paddles of the CF block each disposed over an exposed surface of a respective die, according to an embodiment; [0018] FIG. 9 represents the bond-wireless version of CF block and the LF block of FIG. 8A covered with a die-encapsulation m