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EP-4741845-A1 - VOLTAGE GLITCH DETECTION

EP4741845A1EP 4741845 A1EP4741845 A1EP 4741845A1EP-4741845-A1

Abstract

The disclosure relates to a supply voltage glitch detection circuit (300) comprising: a first flip-flop (301) having a data input (302), a clock input (303) and an output (304); a delay circuit (305) having an output (307) connected to the data input of the first flip-flop; a first clock signal divider (308) having a clock input (309) connected to receive an inverted clock signal and an output (312) connected to an input (306) of the delay circuit (305); a second clock signal divider (313) having a clock input (314) connected to receive the clock signal and an output (315) connected to the clock input (303) of the first flip-flop, wherein the circuit (300) is configured to cause a glitch detection signal output to change state upon a supply voltage of the circuit (300) deviating to cause a change in a delay provided by the delay circuit (305).

Inventors

  • LEE, Hyunsung

Assignees

  • NXP B.V.

Dates

Publication Date
20260513
Application Date
20241108

Claims (15)

  1. A supply voltage glitch detection circuit (300, 400, 500) comprising: a first flip-flop (301) having a data input (302), a clock input (303) and an output (304) for providing a glitch detection signal (OUT); a delay circuit (305) having an input (306) and an output (307) connected to the data input (302) of the first flip-flop (301); a first clock signal divider (308) having a clock input (309) connected to receive an inverted clock signal and an output (312) connected to the input (306) of the delay circuit (305); a second clock signal divider (313) having a clock input (314) connected to receive the clock signal (CLK) and an output (315) connected to the clock input (303) of the first flip-flop (301), wherein the supply voltage glitch detection circuit (300, 400, 500) is configured to cause the glitch detection signal (OUT) to change state upon a supply voltage of the circuit (300, 400, 500) deviating to cause a change in a delay provided by the delay circuit (305).
  2. The supply voltage glitch detection circuit (300, 400, 500) of claim 1, wherein: the first clock signal divider comprises a second flip-flop (308) having a data input (317) and an inverted output (318), the data input (317) connected to the inverted output (318); and the second clock signal divider comprises a third flip-flop (313) having a data input (319) and an inverted output (320), the data input (319) connected to the inverted output (320).
  3. The supply voltage glitch detection circuit (300) of claim 1 or claim 2, comprising an inverter (311) connected between the clock input (309) of the first clock signal divider (308) and a clock signal line (310), wherein the clock input (314) of the second clock signal divider (313) is connected to the clock signal line (310).
  4. The supply voltage glitch detection circuit of any one of claims 1 to 3, wherein the output (312) of the first clock signal divider (308) is connected directly to the input (306) of the delay circuit (305).
  5. The supply voltage glitch detection circuit (400, 500) of claim 2 or claim 3, further comprising a logic AND gate (401) having a first input connected to the output (312) of the second flip-flop (308), a second input connected to the inverted output (320) and data input (319) of the third flip-flop (313) and an output connected to the input (306) of the delay circuit (305).
  6. The supply voltage glitch detector circuit (500) of claim 1, wherein the clock signal is a divided clock signal, the detector circuit (500) further comprising: a third clock signal divider (501) having a clock input (503) connected to receive an inverted clock signal and an output (504) connected to the clock input (309) of the first clock signal divider (308) for providing the inverted divided clock signal to the first clock signal divider (308); and a fourth clock signal divider (502) having a clock input (505) connected to receive the clock signal and an output (506) connected to the clock input (309) of the second clock signal divider (313) for providing the divided clock signal to the second clock signal divider (313).
  7. The supply voltage glitch detector circuit (500) of claim 6, wherein: the third clock signal divider comprises a fourth flip-flop (501) having a data input (507) and an inverted output (508), the data input (507) connected to the inverted output (508); and the fourth clock signal divider comprises a fifth flip-flop (502) having a data input (509) and an inverted output (510), the data input (509) connected to the inverted output (510).
  8. The supply voltage glitch detection circuit (500) of claim 6 or claim 7, comprising an inverter (311) connected between the clock input (503) of the third clock signal divider (501) and a clock signal line (310), wherein the clock input (505) of the fourth clock signal divider (502) is connected to the clock signal line (310).
  9. The supply voltage glitch detection circuit of any one of claims 6 to 8, wherein the output (312) of the first clock signal divider (308) is connected directly to the input (306) of the delay circuit (305).
  10. The supply voltage glitch detection circuit (400, 500) of claim 7 or claim 8, further comprising a logic AND gate (401) having a first input connected to the output (312) of the second flip-flop (308), a second input connected to the inverted output (320) and data input (319) of the third flip-flop (313) and an output connected to the input (306) of the delay circuit (305).
  11. A method of detecting a supply voltage glitch using a detector circuit (300, 400, 500) comprising: a first flip-flop (301) having a data input (302), a clock input (303) and an output (304) for providing a glitch detection signal (OUT); a delay circuit (305) having an input (306) and an output (307) connected to the data input (302) of the first flip-flop (301); a first clock signal divider (308) having a clock input (309) connected to receive an inverted clock signal and an output (312) connected to the input (306) of the delay circuit (305); a second clock signal divider (313) having a clock input (314) connected to receive the clock signal and an output (315) connected to the clock input (303) of the first flip-flop (301), wherein the delay circuit (305) provides a delay of at least half a clock period of a clock signal with a supply voltage of the circuit at a nominal level and, when an increase in the supply voltage causes the delay to fall below half the clock period, the glitch detection signal (OUT) changes state.
  12. The method of claim 11, wherein the delay provided by the delay circuit (305) is at least half of a period of the clock signal (CLK).
  13. The method of claim 11 or claim 12, wherein the first and second clock signal dividers (308, 313) provide a divided clock signal at a respective output (312, 315) having a period of twice the clock signal (CLK) provided at the respective clock inputs (309, 314).
  14. The method of any one of claims 11 to 13, wherein the delay provided by the delay circuit (305) is up to 1.5, 2 or 4 times the period of the clock signal (CLK).
  15. The method of any one of claims 11 to 14, wherein: the first clock signal divider comprises a second flip-flop (308) having a data input (317) and an inverted output (318), the data input (317) connected to the inverted output (318); and the second clock signal divider comprises a third flip-flop (313) having a data input (319) and an inverted output (320), the data input (319) connected to the inverted output (320).

Description

Field The disclosure relates to circuits and methods for detection of voltage glitches. Background Voltage glitches in digital circuits, being temporary increases or decreases in a supply voltage, can be used to extract information from otherwise secure circuits. Intentionally introducing a voltage glitch can inject a fault into a circuit, which can be used to cause the circuit to output sensitive information, for example an internally stored encryption or decryption key. Detecting and/or mitigating the effect of such attacks is therefore an important feature for designing more resilient secure circuits. Summary According to a first aspect there is provided a supply voltage glitch detection circuit comprising: a first flip-flop having a data input, a clock input and an output for providing a glitch detection signal; a delay circuit having an input and an output connected to the data input of the first flip-flop; a first clock signal divider having a clock input connected to receive an inverted clock signal and an output connected to the input of the delay circuit; a second clock signal divider having a clock input connected to receive the clock signal and an output connected to the clock input of the first flip-flop, wherein the voltage glitch detection circuit is configured to cause the glitch detection signal to change state upon a supply voltage of the circuit deviating to cause a change in a delay provided by the delay circuit. In some examples, the first clock signal divider comprises a second flip-flop having a data input and an inverted output, the data input connected to the inverted output; and the second clock signal divider comprises a third flip-flop having a data input and an inverted output, the data input connected to the inverted output. In some examples, the supply voltage glitch detection circuit comprises an inverter connected between the clock input of the first clock signal divider and a clock signal line, wherein the clock input of the second clock signal divider is connected to the clock signal line. In alternative examples, the supply voltage glitch detection circuit comprises an inverter connected between the clock input of the second clock signal divider and a clock signal line, wherein the clock input of the first clock signal divider is connected to the clock signal line. In some examples, the output of the first clock signal divider is connected directly to the input of the delay circuit. In some examples, the supply voltage glitch detection circuit further comprises a logic AND gate having a first input connected to the output of the second flip-flop, a second input connected to the inverted output and data input of the third flip-flop and an output connected to the input of the delay circuit. In some examples, the clock signal is a divided clock signal, the detector circuit further comprising: a third clock signal divider having a clock input connected to receive an inverted clock signal and an output connected to the clock input of the first clock signal divider for providing the inverted divided clock signal to the first clock signal divider; and a fourth clock signal divider having a clock input connected to receive the clock signal and an output connected to the clock input of the second clock signal divider for providing the divided clock signal to the second clock signal divider. In some examples, the third clock signal divider comprises a fourth flip-flop having a data input and an inverted output, the data input connected to the inverted output, and the fourth clock signal divider comprises a fifth flip-flop having a data input and an inverted output, the data input connected to the inverted output. In some examples, the supply voltage glitch detection circuit comprises an inverter connected between the clock input of the third clock signal divider and a clock signal line, wherein the clock input of the fourth clock signal divider is connected to the clock signal line. In some alternative examples, the supply voltage glitch detection circuit comprises an inverter connected between the clock input of the fourth clock signal divider and a clock signal line, wherein the clock input of the third clock signal divider is connected to the clock signal line. The output of the first clock signal divider may be connected directly to the input of the delay circuit. The supply voltage glitch detection circuit may alternatively further comprise a logic AND gate having a first input connected to the output of the second flip-flop, a second input connected to the inverted output and data input of the third flip-flop and an output connected to the input of the delay circuit. According to a second aspect there is provided a method of detecting a supply voltage glitch using a detector circuit comprising: a first flip-flop having a data input, a clock input and an output for providing a glitch detection signal; a delay circuit having an input and an output connected to the data input of