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EP-4741950-A1 - LOW AREA WIDE RANGE TIME TO DIGITAL CONVERTER

EP4741950A1EP 4741950 A1EP4741950 A1EP 4741950A1EP-4741950-A1

Abstract

A time to digital converter including multiple programmable buffers coupled in series for receiving a pulse signal, latches configured to provide binary values indicative of the state of the buffers at the end of a timing pulse asserted on the pulse signal, and a phase converter configured to convert the binary values into a digital output value indicative of a measured delay of the timing pulse. Each of the buffers is configured with an adjustable delay based on a delay select input. The adjustable delay is used to select from among multiple different transition delays of each buffer. The buffers may be configured to be compatible with a standard cell layout. The buffers may be configured as standard cell logic gate with modified connections. The buffers may be calibrated by selecting a fastest delay value that does not cause overflow in response to a calibration pulse.

Inventors

  • Singh, Devesh Pratap
  • Das, Soumyashib
  • UPADHYAY, Manish Kumar

Assignees

  • NXP USA, Inc.

Dates

Publication Date
20260513
Application Date
20251105

Claims (15)

  1. A time to digital converter, comprising: a plurality of programmable buffers coupled in series including a first buffer having an input receiving a pulse signal, wherein each of the plurality of programmable buffers is configured with an adjustable delay based on a delay select input; a plurality of latches, each having an input coupled to an output of a corresponding one of the plurality of buffers, each having a clock input receiving a stop signal, and each having an output configured to provide a corresponding one of a plurality of binary values; and a phase converter configured to convert the plurality of binary values into a digital output value indicative of a measured delay of a timing pulse asserted on the pulse signal.
  2. The time to digital converter of claim 1, wherein the adjustable delay is used to select from among a plurality of different transition delays from an input node to an output node of each of the plurality of programmable buffers.
  3. The time to digital converter of claim 1 or 2, wherein each of the plurality of programmable buffers comprises an input inverting stage coupled between an input node and a middle node and an output inverting stage between the middle node and an output node, and wherein the adjustable delay is configured to select, based on the delay select input, a rising edge delay of the middle node in response to a falling edge of the input node, and to select a falling edge delay of the output node in response to the rising edge delay of the middle node.
  4. The time to digital converter of claim 3, wherein the delay select input comprises a first enable signal and a second enable signal, and wherein each of the plurality of programmable buffers further comprises: a first programmable branch coupled to the middle node configured to adjust the rising edge delay of the middle node based on the first enable signal; and a second programmable branch coupled to the output node configured to adjust the falling edge delay of the output node based on the second enable signal.
  5. The time to digital converter of claim 4, wherein each of the plurality of programmable buffers is configured in complementary MOS (CMOS), wherein the first programmable branch comprises a P-type MOS (PMOS) transistor and an N-type MOS (NMOS) transistor each having a gate terminal receiving the first enable signal, and wherein the second programmable branch comprises a PMOS transistor and an NMOS transistor each having a gate terminal receiving the second enable signal.
  6. The time to digital converter of claim 5, wherein each of the programmable buffers comprises a plurality of CMOS transistors configured in FinFET compact technology.
  7. The time to digital converter of any of claims 3 to 6, wherein the delay select input comprises a first enable signal and a second enable signal, and wherein each of the plurality of programmable buffers further comprises: a first programmable branch coupled to the middle node configured to adjust the rising edge delay of the middle node based on the first enable signal; a second programmable branch coupled to the middle node configured to adjust the rising edge delay of the middle node based on a second enable signal; and a third programmable branch coupled to the output node configured to adjust the falling edge delay of the output node based the second enable signal.
  8. The time to digital converter of claim 7, wherein each of the plurality of programmable buffers is configured in complementary MOS (CMOS), wherein the first programmable branch comprises a P-type MOS (PMOS) transistor and an N-type MOS (NMOS) transistor each having a gate terminal receiving the first enable signal, wherein the second programmable branch comprises a PMOS transistor and an NMOS transistor each having a gate terminal receiving the second enable signal, and wherein the third programmable branch comprises a PMOS transistor and an NMOS transistor each having a gate terminal receiving an inverted version of the second enable signal.
  9. The time to digital converter of claim 8, wherein each of the programmable buffers comprises a plurality of CMOS transistors configured in FinFET technology.
  10. The time to digital converter of any preceding claim, wherein each of the plurality of programmable buffers is configured to be compatible with a standard cell layout.
  11. The time to digital converter of any preceding claim, further comprising: a controller configured to calibrate the plurality of programmable buffers by applying a calibration pulse on the pulse signal, adjusting a delay select signal provided to the delay select inputs of the plurality of programmable buffers, and selecting a fastest value of the delay select signal that does not cause overflow of the plurality of programmable buffers in response to the calibration pulse.
  12. A method of converting time to a digital value, comprising: providing a plurality of programmable buffers coupled in series including a first buffer having an input receiving a pulse signal, wherein each of the plurality of programmable buffers is configured with an adjustable delay based on a delay select input; asserting a timing pulse on the pulse signal, wherein the timing pulse has a leading edge and a trailing edge; latching outputs of the plurality of programmable buffers in response to the trailing edge of the timing pulse and providing a corresponding plurality of binary values; and converting the plurality of binary values into a digital output value indicative of a duration of the timing pulse.
  13. The method of claim 12, further comprising providing a delay select signal to the delay select input of each of the plurality of programmable buffers to select from among a plurality of different transition delays from an input node to an output node of each of the plurality of programmable buffers.
  14. The method of claim 12 or 13, wherein said providing a plurality of programmable buffers comprises providing an input inverting stage coupled between an input node and a middle node and an output inverting stage between the middle node and an output node for each of the plurality of programmable buffers; and providing a delay select signal to the delay select input of each of the plurality of programmable buffers to select a rising edge delay of the middle node in response to a falling edge of the input node and to select a falling edge delay of the output node in response to the rising edge delay of the middle node for each of the plurality of programmable buffers.
  15. The method of claim 14, wherein said providing a plurality of programmable buffers further comprises, for each of the plurality of programmable buffers: providing a first programmable branch coupled to the middle node configured to adjust the rising edge delay of the middle node based on a first enable signal; and providing a second programmable branch coupled to the output node configured to adjust the falling edge delay of the output node based on a second enable signal; and providing the first and second enable signals to the delay select input of each of the plurality of programmable buffers to select from among a plurality of different transition delays from an input node to an output node of each of the plurality of programmable buffers.

Description

BACKGROUND FIELD The present disclosure relates in general to time to digital conversion, and more particularly to a low area, wide range time to digital converter. DESCRIPTION OF THE RELATED ART A time to digital converter (TDC) has versatile use in clock and voltage measurement circuits. For measuring clock signals on a system-on-chip (SoC), a TDC might require a wide input clock frequency range to handle a wide range of frequencies present on SoC, such as from the megahertz (MHz) frequency range to the gigahertz (GHz) frequency range. Delay line based TDCs are frequently used in clock bult-in, self-test (BIST) and other time measurement circuits which require relatively good resolution. The delay line may be formed by a series of substantially identical unit delays, in which the unit delay should be as small as reasonably available. The delay line may be implemented using digital standard cells, which reduces overall area as compared to using analog delay cells. Analog type or differential delay elements require larger power and area. The advent of the fin field-effect transistor (finFET) process have benefitted digital delay units with lower delays. Standard cell-based unit delay cells can achieve reasonable delays within a very compact area but have a lower limit especially at slow process-voltage-temperature (PVT) corners. The variation across PVT corners, however, requires a relatively long delay line in order to cater to wide types of inputs (e.g., various clocks provided on typical SoC configurations). The base unit delay using a standard cell inverter between the fast corner and the slow corner varies by as much as a factor of two. Having a larger unit delay would degrade the resolution further on the slow corner. In order to increase measured input time range by two while maintaining resolution for a conventional configuration, the delay line length would need to be doubled consuming valuable space and reducing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the present invention are illustrated by way of example and are not limited by the accompanying figures. Similar references in the figures may indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. FIG. 1 is a simplified schematic and block diagram of a time to digital converter (TDC) implemented according to one embodiment.FIG. 2 is a timing diagram illustrating operation of the TDC of FIG. 1 according to one embodiment for measuring a period of a clock signal under test.FIG. 3 is a detailed schematic diagram of a delay line of FIG. 2 implemented according to one embodiment which may be used as the delay line of FIG. 1.FIG. 4 is a schematic diagram of a portion of a delay line implemented according to an alternative embodiment which may be used as the delay line of FIG. 1.FIG. 5 is a schematic diagram of a programmable buffer implemented according to one embodiment that may be used as any one up to all of the buffers B1 - BN of the delay line of FIG. 1.FIG. 6 is a tabular diagram illustrating exemplary delay times of a specific implementation of the buffer of FIG. 5 based on settings of the enable signals of DSEL for the fastest and slowest corners of process-voltage-temperature (PVT) according to one embodiment.FIG. 7 is a plot of delay times of the buffer of FIG. 5 (having a specific implementation as that for FIG. 6) for each of the four settings of the enable signals of DSEL (00b, 01b, 10b, 11b) for various PVT conditions according to one embodiment.FIG. 8 is a schematic diagram of a programmable buffer implemented according to another embodiment that may be used as any one up to all of the buffers B1 - BN of the delay line of FIG. 1.FIG. 9 is a flowchart diagram illustrating a delay line measurement test procedure according to one embodiment that may be used to determine the total timing of the delay line of FIG. 1 for a given implementation.FIG. 10 is a flowchart diagram illustrating a first calibration procedure for calibrating the delay line of FIG. 1 according to one embodiment.FIG. 11 is a flowchart diagram illustrating a second calibration procedure for calibrating the delay line of FIG. 1 according to another embodiment.FIG. 12 is a diagram of a standard cell structure configured to implement the buffer of FIG. 5 according to one embodiment. DETAILED DESCRIPTION A time to digital converter as described herein includes multiple programmable buffers coupled in series for receiving a pulse signal, latches configured to provide binary values indicative of the state of the buffers at the end of a timing pulse asserted on the pulse signal, and a phase converter configured to convert the binary values into a digital output value indicative of a measured delay of the timing pulse. Each of the buffers is configured with an adjustable delay based on a delay select input. The adjustable delay is used to select from among multiple different tran