EP-4741985-A1 - REFERENCE CURRENT GENERATOR FOR NON-VOLATILE MEMORY

EP4741985A1EP 4741985 A1EP4741985 A1EP 4741985A1EP-4741985-A1

Abstract

A reference current generator includes two transistors, a resistor and a mirroring circuit. The first transistor includes a source receiving a supply voltage, a drain connected with a first node, and a gate connected with a second node. The second transistor includes a source receiving the supply voltage, and a drain and a gate connected with a third node. The resistor is connected between the second node and the third node. The mirroring circuit includes an input terminal receiving an input current, a first mirrored terminal connected with the second node and a second mirrored terminal connected with the first node. The first mirrored terminal and the second mirrored terminal generate a first mirroring current and a second mirroring current respectively. The first transistor generates a saturation current. A reference current is equal to the saturation current minus the second mirroring current.

Inventors

CHANG, CHE-WEI
KU, WEI-MING

Assignees

eMemory Technology Inc.

Dates

Publication Date: 20260513
Application Date: 20251107

Claims (13)

A reference current generator (200) for a non-volatile memory, the reference current generator (200) comprising: a first transistor (M A ), wherein a source terminal of the first transistor (M A ) receives a first supply voltage (V DD ), a drain terminal of the first transistor is connected with a first node (a), and a gate terminal of the first transistor is connected with a second node (b); a second transistor (M B ), wherein a source terminal of the second transistor (M B ) receives the first supply voltage (V DD ), a drain terminal of the second transistor (M B ) is connected with a third node (c), and a gate terminal of the second transistor is connected with the third node (c); a first resistor (R POLY1 ), wherein a first terminal of the first resistor (R POLY1 ) is connected with the third node (c), and a second terminal of the first resistor (R POLY1 ) is connected with the second node (b); and a first mirroring circuit (210), wherein an input terminal of the first mirroring circuit (210) receives an input current (I IN ), a first mirrored terminal of the first mirroring circuit (210) is connected with the second node (b), and a second mirrored terminal of the first mirroring circuit (210) is connected with the first node (a), wherein the first mirrored terminal of the first mirroring circuit (210) generates a first mirroring current (I M1 ), the second mirrored terminal of the first mirroring circuit (210) generates a second mirroring current (I M2 ), and there is a first proportional relationship between the input current (I IN ), the first mirroring current (I M1 ) and the second mirroring current (I M2 ); wherein the first transistor (M A ) and the second transistor (M B ) are operated in a saturation mode, and the first transistor (M A ) generates a saturation current (I A ), wherein the reference current generator (100) outputs a first reference current (I REF ), and the first reference current (I REF ) is equal to the saturation current (I A ) minus the second mirroring current (I M2 ).
The reference current generator as claimed in claim 1, wherein an over-drive voltage of the first transistor is at least five times a voltage drop across the first resistor, and the over-drive voltage of the first transistor is equal to a source-gate voltage of the first transistor plus a threshold voltage of the first transistor.
The reference current generator as claimed in claim 1 or 2, wherein the first mirroring circuit comprises: a third transistor, wherein a drain terminal of the third transistor receives the input current, a gate terminal of the third transistor is connected with the drain terminal of the third transistor, and a source terminal of the third transistor receives a second supply voltage; a fourth transistor, wherein a drain terminal of the fourth transistor is connected with the second node, a gate terminal of the fourth transistor is connected with the gate terminal of the third transistor, and a source terminal of the fourth transistor receives the second supply voltage; and a fifth transistor, wherein a drain terminal of the fifth transistor is connected with the first node, a gate terminal of the fifth transistor is connected with the gate terminal of the third transistor, and a source terminal of the fifth transistor receives the second supply voltage, wherein the first supply voltage is higher than the second supply voltage.
The reference current generator as claimed in anyone of the claims 1 to 3, further comprising a current source, wherein the current source generates the input current, and the input current is inputted into the input terminal of the mirroring circuit.
The reference current generator as claimed in claim 1, further comprising: a bandgap reference circuit generating a bandgap voltage; a second resistor, wherein a first terminal of the second resistor is connected with a fourth node and a second terminal of the receives a second supply voltage; a second mirroring circuit, wherein an input terminal of the second mirroring circuit is connected with the fourth node to receive a first current, and a mirrored terminal of the second mirroring circuit generates the input current; and an operational amplifier, wherein an inverting input terminal of the operational amplifier receives the bandgap voltage, a non-inverting input terminal of the operational amplifier is connected with the fourth node, and an output terminal is connected with the second mirroring circuit to control the second mirroring circuit.
The reference current generator as claimed in claim 5, wherein the first current is equal to the bandgap voltage divided by a resistance of the second resistor, and there is a second proportional relationship between the first current and the input current.
The reference current generator as claimed in claim 5 or 6, wherein the first resistor and the second resistor are polysilicon resistors.
The reference current generator as claimed in anyone of the claims 5 to 7, wherein the second mirroring circuit comprises: a third transistor, wherein a source terminal of the third transistor receives the first supply voltage, a gate terminal of the third transistor is connected with the output terminal of the operational amplifier, and a drain terminal of the third transistor is connected with the fourth node; and a fourth transistor, wherein a source terminal of the fourth transistor receives the first supply voltage, a gate terminal of the fourth transistor is connected with the output terminal of the operational amplifier, and a drain terminal of the fourth generates the input current; wherein the first supply voltage is higher than the second supply voltage.
The reference current generator as claimed in claim 1, further comprising a second mirroring circuit, wherein an input terminal of the second mirroring circuit is connected with the first node to receive the first reference current, and a mirrored terminal of the second mirroring circuit generates a second reference current, wherein there is a second proportional relationship between the first reference current and the second reference current.
The reference current generator as claimed in claim 9, wherein the second mirroring circuit comprises: a third transistor, wherein a drain terminal of the third transistor is connected with the first node to receive the first reference current, a gate terminal of the third transistor is connected with the drain terminal of the third transistor, and a source terminal of the third transistor receives a second supply voltage; and a fourth transistor, wherein a drain terminal of the fourth transistor is served as the mirrored terminal of the second mirroring circuit to generate the second reference current, a gate terminal of the fourth transistor is connected with the gate terminal of the third transistor, and a source terminal of the fourth transistor receives the second supply voltage, wherein the first supply voltage is higher than the second supply voltage.
The reference current generator as claimed in claim 9 or 10, wherein the second mirroring circuit comprises: a third transistor, wherein a drain terminal of the third transistor is connected with the first node to receive the first reference current, a gate terminal of the third transistor is connected with the drain terminal of the third transistor, and a source terminal of the third transistor receives a second supply voltage; a fourth transistor, wherein a gate terminal of the fourth transistor is connected with the gate terminal of the third transistor, and a source terminal of the fourth transistor receives the second supply voltage; a fifth transistor, wherein a drain terminal of the fifth transistor is connected with a drain terminal of the fourth transistor, a gate terminal of the fifth transistor is connected with the drain terminal of the fifth transistor, and a source terminal of the fifth transistor receives the second supply voltage; and a sixth transistor, wherein a drain terminal of the sixth transistor is served as the mirrored terminal of the second mirroring circuit to generate the second reference current, a gate terminal of the sixth transistor is connected with the gate terminal of the fifth transistor, and a source terminal of the sixth transistor receives the second supply voltage, wherein the first supply voltage is higher than the second supply voltage.
The reference current generator as claimed in anyone of the claims 9 to 11, wherein the non-volatile memory comprises a memory cell and a sensing circuit, wherein when a read action is performed, the sensing circuit receives a cell current from the memory cell and the second reference current from the reference current generator, and the sensing circuit determines a storage state of the memory cell according to the cell current and the second reference current.
The reference current generator as claimed in claim 12, wherein if the cell current is higher than the second reference current, the sensing circuit determines that the memory cell is in a programmed state, wherein if the cell current is lower than the second reference current, the sensing circuit determines that the memory cell is in an erased state.

Description

FIELD OF THE INVENTION The present invention relates to a current generator, and more particularly to a reference current generator for a non-volatile memory. BACKGROUND OF THE INVENTION As is well known, a non-volatile memory includes a memory cell array. The memory cell array is composed of a plurality of non-volatile memory cells. Each non-volatile memory cell includes a storage unit. For example, the storage unit is a floating gate transistor. The storage state of the non-volatile memory cell is determined according to the number of carriers stored in the floating gate of the floating gate transistor. For example, the floating gate transistor is a P-type floating gate transistor, and the carriers are electrons. When a program action is performed on the memory cell, electrons are controlled to be injected into the floating gate of the floating gate transistor. Meanwhile, carriers are stored in the floating gate, and the memory cell is in a programmed state or an on state. When an erase action is performed on the memory cell, electrons are controlled to be ejected from the floating gate of the floating gate transistor. Meanwhile, carriers are not stored in the floating gate, and the memory cell is in an erased state or an off state. The on state and the off state represent two different storage states of the memory cell. Alternatively, the floating gate transistor is an N-type floating gate transistor. By controlling the number of carriers stored in the floating gate of the floating gate transistor, the memory cell is selectively in the on state or the off state. Furthermore, when a read action is performed on the memory cell, the memory cell in the on state generates a larger cell current (also referred to as an on current), and the memory cell in the off state generates a smaller cell current (also referred to as an off current). That is, when the read action is performed, the storage state of the memory cell can be determined according to the magnitude of the cell current generated by the memory cell. In order to determine the storage state of the memory cell, the non-volatile memory is equipped with a reference current generator and a sensing circuit. The reference current generator generates a reference current. The magnitude of the reference current is set to be in the range between the on current and the off current. When the read action is performed, the sensing circuit receives the reference current and the cell current generated by the memory cell and determines the storage state of the memory cell. If the cell current is higher than the reference current, the sensing circuit determines that the memory cell is in the programmed state or the on state. If the cell current is lower than the reference current, the sensing circuit determines that the memory cell is in the erased state or the off state. Generally, after the non-volatile memory is manufactured and tested, it can be determined which process corner the non-volatile memory belongs to. Furthermore, different process corners of the memory cells and different operating temperatures will affect the magnitude of the cell current. FIG. 1 schematically illustrates the relationships between the cell current and the reference current at various process corners and various operating temperatures for the conventional non-volatile memory. After all memory cells at a typical-typical corner (also referred to as a TT corner) are read and subjected to a statistics analysis, the following data are obtained. At the operating temperature of -40°C, the minimum on current (Min. ION) of the memory cells in the on state is about 18 µA, and the maximum off current (Max. IOFF) of the memory cell in the off state is about 1 µA. At the operating temperature of 25°C, the minimum on current of the memory cells in the on state is about 16 µA, and the maximum off current of the memory cell in the off state is about 1 µA. At the operating temperature of 150°C, the minimum on current of the memory cells in the on state is about 14 µA, and the maximum off current of the memory cell in the off state is about 2 µA. After all memory cells at a fast-fast corner (also referred to as an FF corner) are read and subjected to a statistics analysis, the following data are obtained. At the operating temperature of -40°C, the minimum on current of the memory cells in the on state is about 20 µA, and the maximum off current of the memory cell in the off state is about 1 µA. At the operating temperature of 25°C, the minimum on current of the memory cells in the on state is about 18 µA, and the maximum off current of the memory cell in the off state is about 2 µA. At the operating temperature of 150°C, the minimum on current of the memory cells in the on state is about 14 µA, and the maximum off current of the memory cell in the off state is about 3 µA. After all memory cells at a slow-slow corner (also referred to as an SS corner) are read and subjected to a statistics analysis, the fo