EP-4742026-A2 - MANAGING OPERATIONS IN MEMORY SYSTEMS

Abstract

In certain aspects, a system includes a memory device and a controller. The controller is configured to: perform data transfer to the memory device for a first operation corresponding to a first command, wherein performing the data transfer to the memory device comprises transferring a plurality of allocation units of data; and send a second command to the memory device while performing the data transfer and the data transfer in a current allocation unit is completed, wherein the current allocation unit is not a last allocation unit of the plurality of allocation units of data; and the memory device is configured to: allocate a first buffer space for the first operation; allocate a second buffer space for a second operation corresponding to the second command; and return an execution result after performing the second operation to the controller.

Inventors

• LIU, WEILIN

Assignees

• Yangtze Memory Technologies Co., Ltd.

Dates

Publication Date

20260513

Application Date

20230307

Claims (15)

1. A system comprising: a memory device; and a controller, wherein: the controller is configured to: perform data transfer to the memory device for a first operation corresponding to a first command, wherein performing the data transfer to the memory device comprises transferring a plurality of allocation units of data; and send a second command to the memory device while performing the data transfer and the data transfer in a current allocation unit is completed, wherein the current allocation unit is not a last allocation unit of the plurality of allocation units of data; and the memory device is configured to: allocate a first buffer space for the first operation; allocate a second buffer space for a second operation corresponding to the second command; and return an execution result to the controller after performing the second operation.
2. The system of claim 1, wherein the first buffer space allocated for the first operation is different from the second buffer space allocated for the second operation.
3. The system of claim 1, wherein the controller is configured to: in response to that the data transfer in the current allocation unit is not completed, wait for the data transfer in the current allocation unit to be completed.
4. The system of claim 1, wherein the controller is configured to send a third command to suspend the data transfer before sending the second command to the memory device.
5. The system of claim 1, wherein each allocation unit has a size that is smaller than a page size.
6. The system of claim 1, wherein each allocation unit has a size that is equal to one fourth of a page size.
7. The system of claim 1, wherein the controller is configured to: in response to receiving the execution result of the second operation from the memory device, send a resume command to the memory device to resume the first operation; and wherein the memory device is configured to: in response to receiving the resume command from the controller, continue the data reception for the first operation.
8. The system of claim 7, wherein the memory device is further configured to: in response to receiving the resume command from the controller, restore context of the first operation from the first buffer space.
9. The system of claim 1, wherein the controller is configured to: in response to receiving the execution result of the second operation from the memory device, send an abort command to the memory device to abort the first operation; and wherein the memory device is configured to: in response to receiving the abort command from the controller, release the first buffer space that has previously been allocated for the first operation.
10. The system of claim 1, wherein the controller is configured to: in response to completing the second operation, release the second buffer space allocated for the second operation.
11. A method performed by a system comprising a memory device and a controller, wherein the method comprises: performing data transfer to the memory device for a first operation corresponding to a first command, wherein performing the data transfer to the memory device comprises transferring a plurality of allocation units of data; allocating, by the memory device, a first buffer space for the first operation; sending, by the controller, a second command to the memory device while performing the data transfer and that data transfer in a current allocation unit is completed; allocating, by the memory device, a buffer space for a second operation corresponding to the second command; performing, by the memory device, the second operation using the buffer space allocated for the second operation; and returning, by the memory device, an execution result of the second operation to the controller.
12. The method of claim 11, further comprising: in response to that the data transfer in the current allocation unit is not completed, waiting for the data transfer in the current allocation unit to be completed.
13. The method of claim 11, wherein the first buffer space allocated for the first operation is different from the second buffer space allocated for the second operation.
14. The method of claim 11, further comprising: in response to receiving the execution result of the second command from the memory device, sending, by the controller, a resume command to the memory device to resume the first operation; and in response to receiving the resume command from the controller, continuing, by the memory device, the data reception for the first operation.
15. The method claim11, further comprising: in response to receiving the execution result of the second operation from the memory device, sending, by the controller, an abort command to the memory device to abort the first operation; and in response to receiving the abort command from the controller, releasing, by the memory device, the first buffer space that has previously been allocated for the first operation.

Description

TECHNICAL FIELD The present disclosure generally relates to a memory system, and more specifically, to management of suspend and resume operations of a memory system. BACKGROUND A memory system can include one or more memory components that store data. The memory components can be, for example, non-volatile memory components and volatile memory components. In general, a host system can utilize a memory system to store data in the memory components and retrieve data from the memory components. SUMMARY The present disclosure describes management of suspend and resume operations in a memory system. In one aspect, for example, the present disclosure describes a system that includes a memory device and a controller. The controller is configured to: while performing data transfer to the memory device for a first operation corresponding to a first command, check whether a second command is received, wherein performing the data transfer to the memory device comprises performing the data transfer in terms of allocation units (AUs); and in response to determining that the second command is received and that data transfer in a current AU is completed, send a suspend command to the memory device. The memory device is configured to: in response to receiving the suspend command from the controller, suspend data reception for the first operation; allocate a buffer space for a second operation corresponding to the second command; perform the second operation using the buffer space allocated for the second operation; and return an execution result of the second operation to the controller. In another aspect, the present disclosure describes a method performed by a system that includes a memory device and a controller. The method includes: while performing data transfer to the memory device for a first operation corresponding to a first command, checking, by the controller, whether a second command is received, wherein performing the data transfer to the memory device comprises performing the data transfer in terms of AUs; in response to determining that the second command is received and that data transfer in a current AU is completed, sending, by the controller, a suspend command to the memory device; in response to receiving the suspend command from the controller, suspending, by the memory device, data reception for the first operation; allocating, by the memory device, a buffer space for a second operation corresponding to the second command; performing, by the memory device, the second operation using the buffer space allocated for the second operation; and returning, by the memory device, an execution result of the second operation to the controller. In another aspect, the present disclosure describes a controller for controlling a memory device. The controller includes at least one processor coupled to at least one memory storing programming instructions that, when executed by the at least one processor, cause the controller to perform operations comprising: while performing data transfer to the memory device for a first operation corresponding to a first command, checking whether a second command is received, wherein performing the data transfer to the memory device comprises performing the data transfer in terms of AUs; and in response to determining that the second command is received and that data transfer in a current AU is completed, sending a suspend command to the memory device. In still another aspect, the present disclosure describes a memory device. The memory device includes at least one processor coupled to at least one memory storing programming instructions; at least one internal memory; at least one buffer space; and an array of memory cells, and wherein the programming instructions, when executed by the at least one processor, cause the memory device to perform operations comprising: while performing data reception from a controller for a first operation corresponding to a first command, receiving a suspend command from the controller to suspend the data reception; in response to receiving the suspend command from the controller, suspending the data reception for the first operation; allocating a buffer space of the at least one buffer space for a second operation corresponding to a second command; performing the second operation using the buffer space allocated for the second operation; and returning an execution result of the second operation to the controller. The details of one or more implementations of the subject matter of this disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a block diagram of an example system having a memory device, in accordance with some aspects of the present disclosure.FIG. 2A illustrates a diagram of an example memory card having a memory device, in acc