EP-4742028-A2 - SYSTEM ON CHIP SUPPORTING MULTI-SCREEN DISPLAY, SYNCHRONIZATION METHOD FOR MULTI-SCREEN DISPLAY, AND ELECTRONIC DEVICE

Abstract

A system on chip includes: a processor core configured to perform a write operation on a synchronization control register of a timing generator corresponding to a display screen performing multi-screen display, enable a display synchronization function of the timing generator, and divide the timing generator into a master timing generator or a slave timing generator; wherein the master timing generator is configured to generate a first timing synchronization signal, transmit the first timing synchronization signal to a display screen corresponding to the master timing generator, and transmit a vertical synchronization signal of the first timing synchronization signal to the slave timing generator; and the slave timing generator is configured to generate a second timing synchronization signal in response to the vertical synchronization signal transmitted by the master timing generator, and transmit the second timing synchronization signal to a display screen corresponding to the slave timing generator.

Inventors

• LIN, TAO
• LI, XINLEI

Assignees

• XG TECH PTE. LTD.

Dates

Publication Date

20260513

Application Date

20260331

Claims (15)

1. A system on chip supporting multi-screen display, characterized by comprising: a processor core configured to perform a write operation on a synchronization control register of a timing generator corresponding to a display screen performing multi-screen display, to enable a display synchronization function of the timing generator, and divide the timing generator into a master timing generator or a slave timing generator; wherein the master timing generator is configured to generate a first timing synchronization signal, transmit the first timing synchronization signal to a display screen corresponding to the master timing generator, and transmit a vertical synchronization signal of the first timing synchronization signal to the slave timing generator; and the slave timing generator is configured to generate a second timing synchronization signal in response to the vertical synchronization signal transmitted by the master timing generator, and transmit the second timing synchronization signal to a display screen corresponding to the slave timing generator.
2. The system on chip according to claim 1, wherein synchronization control flag bits in the synchronization control register comprise one or more of a synchronization enable flag bit, a timing generator type flag bit, a master timing generator flag bit, a synchronization state switching flag bit, a synchronization alignment flag bit, a synchronization loss flag bit, and a synchronization delay flag bit.
3. The system on chip according to claim 2, wherein the processor core is configured to perform a set operation on the synchronization enable flag bit in a first synchronization control register corresponding to a first timing generator among the timing generators, to enable a display synchronization function of the first timing generator, and perform a set operation on the timing generator type flag bit in the first synchronization control register, to set the first timing generator as the master timing generator; and the processor core is further configured to perform a set operation on the synchronization enable flag bit in a second synchronization control register corresponding to a second timing generator among the timing generators, to enable a display synchronization function of the second timing generator, and perform a set operation on the timing generator type flag bit in the second synchronization control register, to set the second timing generator as the slave timing generator.
4. The system on chip according to claim 3, wherein the processor core is configured to set a parameter value of a master timing generator flag bit in the second synchronization control register corresponding to the second timing generator to a timing generator identifier corresponding to the first timing generator; and the second timing generator is configured to generate a second timing synchronization signal in response to the vertical synchronization signal transmitted by the first timing generator, and transmit the second timing synchronization signal to a display screen corresponding to the second timing generator.
5. The system on chip according to any one of claims 2 to 4, wherein the processor core is further configured to set a parameter value of the synchronization delay flag bit in the synchronization control register corresponding to the slave timing generator to a number of synchronization delay lines; and the slave timing generator is configured to generate the second timing synchronization signal, after delaying the number of synchronization delay lines of horizontal synchronization signals, in response to the vertical synchronization signal transmitted by the master timing generator, and transmit the second timing synchronization signal to the display screen corresponding to the slave timing generator.
6. The system on chip according to any one of claims 2 to 5, wherein the processor core is further configured to perform a set operation on the synchronization state switching flag bit in the synchronization control register corresponding to the slave timing generator, to stop a display synchronization between the slave timing generator and the master timing generator; and the slave timing generator is configured to generate a third timing synchronization signal, and transmit the third timing synchronization signal to the display screen corresponding to the slave timing generator.
7. The system on chip according to claim 2 or 6, wherein the processor core is further configured to perform a set operation on the synchronization state switching flag bit in the synchronization control register corresponding to the slave timing generator, to restore the display synchronization between the slave timing generator and the master timing generator, perform a set operation on the synchronization alignment flag bit in the synchronization control register, to enable the slave timing generator to perform display synchronization alignment with the master timing generator in a next image frame, and perform a set operation on the synchronization loss flag bit in the synchronization control register, to enable the slave timing generator to output a black frame when the display synchronization with the master timing generator is lost; the slave timing generator is configured to generate a fourth timing synchronization signal in response to a loss of display synchronization with the master timing generator, and transmit the fourth timing synchronization signal to a display screen corresponding to the slave timing generator; wherein the fourth timing synchronization signal is used to instruct the second display screen to display a black frame; and the slave timing generator is further configured to generate a second timing synchronization signal in response to the vertical synchronization signal transmitted by the master timing generator in a next image frame, and transmit the second timing synchronization signal to the display screen corresponding to the slave timing generator.
8. A synchronization method for multi-screen display based on a system on chip, characterized by comprising: performing, by a processor core, a write operation on a synchronization control register of a timing generator corresponding to a display screen performing multi-screen display, to enable a display synchronization function of the timing generator, and divide the timing generator into a master timing generator and a slave timing generator; generating, by the master timing generator, a first timing synchronization signal, transmitting the first timing synchronization signal to a display screen corresponding to the master timing generator, and transmitting a vertical synchronization signal of the first timing synchronization signal to the slave timing generator; and generating, by the slave timing generator, a second timing synchronization signal in response to the vertical synchronization signal transmitted by the master timing generator, and transmitting the second timing synchronization signal to a display screen corresponding to the slave timing generator.
9. The method according to claim 8, wherein synchronization control flag bits in the synchronization control register comprise one or more of a synchronization enable flag bit, a timing generator type flag bit, a master timing generator flag bit, a synchronization state switching flag bit, a synchronization alignment flag bit, a synchronization loss flag bit, and a synchronization delay flag bit.
10. The method according to claim 9, wherein performing, by a processor core, a write operation on a synchronization control register of a timing generator corresponding to a display screen performing multi-screen display comprises: performing a set operation on the synchronization enable flag bit in a first synchronization control register corresponding to a first timing generator among the timing generators, to enable a display synchronization function of the first timing generator, and perform a set operation on the timing generator type flag bit in the first synchronization control register, to set the first timing generator as the master timing generator; and performing a set operation on the synchronization enable flag bit in a second synchronization control register corresponding to a second timing generator among the timing generators, to enable a display synchronization function of the second timing generator, and performing a set operation on the timing generator type flag bit in the second synchronization control register, to set the second timing generator as the slave timing generator.
11. The method according to claim 10, wherein performing a set operation on the timing generator type flag bit in the first synchronization control register, to set the first timing generator as the master timing generator comprises: setting a parameter value of a master timing generator flag bit in the second synchronization control register corresponding to the second timing generator to a timing generator identifier corresponding to the first timing generator; and wherein generating, by the slave timing generator, a second timing synchronization signal in response to the vertical synchronization signal transmitted by the master timing generator, and transmitting the second timing synchronization signal to a display screen corresponding to the slave timing generator comprises generating a second timing synchronization signal in response to the vertical synchronization signal transmitted by the first timing generator, and transmitting the second timing synchronization signal to a display screen corresponding to the second timing generator.
12. The method according to any one of claims 9 to 11, wherein performing, by a processor core, a write operation on a synchronization control register of a timing generator corresponding to a display screen performing multi-screen display comprises setting a parameter value of the synchronization delay flag bit in the synchronization control register corresponding to the slave timing generator to a number of synchronization delay lines; and generating, by the slave timing generator, a second timing synchronization signal in response to the vertical synchronization signal transmitted by the master timing generator, and transmitting the second timing synchronization signal to a display screen corresponding to the slave timing generator comprises generating the second timing synchronization signal, after delaying the number of synchronization delay lines of horizontal synchronization signals, in response to the vertical synchronization signal transmitted by the master timing generator, and transmitting the second timing synchronization signal to the display screen corresponding to the slave timing generator.
13. The method according to any one of claims 9 to 12, wherein performing, by a processor core, a write operation on a synchronization control register of a timing generator corresponding to a display screen performing multi-screen display comprises performing a set operation on the synchronization state switching flag bit in the synchronization control register corresponding to the slave timing generator, to stop a display synchronization between the slave timing generator and the master timing generator; and wherein generating, by the slave timing generator, a second timing synchronization signal in response to the vertical synchronization signal transmitted by the master timing generator, and transmitting the second timing synchronization signal to a display screen corresponding to the slave timing generator comprises generating a third timing synchronization signal, and transmit the third timing synchronization signal to the display screen corresponding to the slave timing generator.
14. An electronic device, characterized by comprising a display screen and the system on chip supporting multi-screen display according to any one of claims 1 to 7, wherein the display screen is configured to perform multi-screen display based on a first timing synchronization signal output from a master timing generator and a second timing synchronization signal output from a slave timing generator in the system on chip.
15. A computer readable storage medium, characterized by storing a computer program thereon, which, when executed by a processor, causes the processor to perform the synchronization method for multi-screen display based on a system on chip according to any one of claims 8 to 13.

Description

FIELD OF THE PRESENT DISCLOSURE The present disclosure relates to the technical field of intelligent driving technology, and in particular, to a system on chip supporting multi-screen display, a synchronization method for multi-screen display, and an electronic device. BACKGROUND OF THE PRETRANSMITTED DISCLOSURE With the rapid development of intelligent driving technology, vehicle cockpit systems are evolving towards the trend of multi-screen, high interactivity and high immersion. At present, most mainstream intelligent cockpit chip architectures adopt a fusion architecture of dual operating systems of Android and QNX. To avoid the complexity and performance overhead caused by the transmission of timing synchronization signals across operating systems, intelligent cockpit chips mainly realize the display synchronization among multiple screens through a coordination mechanism at the software layer. However, the display synchronization accuracy among multiple screens is affected by the coordination delay of the software layer. Especially in scenarios with high frame rate and multi-screen display (i.e., multiple display screens are spliced into one display screen), the display images among multiple display screens cannot be strictly synchronized due to the coordination delay of the software layer,, resulting in obvious misalignment or smear phenomenon in the human eye vision of multiple display screens, which seriously affects the visual experience. Therefore, there is an urgent need for a method capable of improving the display synchronization accuracy of multi-screen display. SUMMARY OF THE PRESENT DISCLOSURE To solve the above technical problems, the present disclosure provides a system on chip supporting multi-screen display, a synchronization method for multi-screen display, and an electronic device to improve the display synchronization accuracy of multi-screen display. According to an embodiment of a first aspect of the present disclosure, there is provided a system on chip supporting multi-screen display, including: a processor core configured to perform a write operation on a synchronization control register of a timing generator corresponding to a display screen performing multi-screen display, to enable a display synchronization function of the timing generator, and divide the timing generator into a master timing generator and a slave timing generator; wherethe master timing generator is configured to generate a first timing synchronization signal, transmit the first timing synchronization signal to a display screen corresponding to the master timing generator, and transmit a vertical synchronization signal of the first timing synchronization signal to the slave timing generator; andthe slave timing generator is configured to generate a second timing synchronization signal in response to the vertical synchronization signal transmitted by the master timing generator, and transmit the second timing synchronization signal to a display screen corresponding to the slave timing generator. According to an embodiment of a second aspect of the present disclosure, there is provided a synchronization method for multi-screen display based on a system on chip, including: performing, by a processor core, a write operation on a synchronization control register of a timing generator corresponding to a display screen performing multi-screen display, to enable a display synchronization function of the timing generator, and divide the timing generator into a master timing generator and a slave timing generator;generating, by the master timing generator, a first timing synchronization signal, transmitting the first timing synchronization signal to a display screen corresponding to the master timing generator, and transmitting a vertical synchronization signal of the first timing synchronization signal to the slave timing generator; andgenerating, by the slave timing generator, a second timing synchronization signal in response to the vertical synchronization signal transmitted by the master timing generator, and transmit the second timing synchronization signal to a display screen corresponding to the slave timing generator. According to an embodiment of a third aspect of the present disclosure, there is provided an electronic device, including a display screen and the system on chip supporting multi-screen display provided according to the embodiment of the first aspect; the display screen is configured to perform multi-screen display based on a first timing synchronization signal output from a master timing generator and a second timing synchronization signal output from a slave timing generator in the system on chip. According to an embodiment of a fourth aspect of the present disclosure, there is provided a computer readable storage medium, storing a computer program, which, when executed by a processor, causes the processor to perform the synchronization method for multi-screen display based on a system on chip