EP-4742035-A1 - COMPUTING APPARATUS AND RELATED TASK EXECUTION SCHEDULING METHOD

Abstract

Embodiments of this application disclose a computing apparatus and a related task execution scheduling method. The computing apparatus may include a scheduling module, an interrupt controller, and at least one processor core. The scheduling module is configured to schedule N tasks. The interrupt controller is configured to schedule M interrupts. The N tasks and the M interrupts are marked by using unified priorities, one task corresponds to one priority, and one interrupt corresponds to one priority. A target processor core in the at least one processor core is configured to: receive and run a target task sent by the scheduling module, where the target task is one of the N tasks; and receive a target interrupt sent by the interrupt controller, and if a priority corresponding to the target interrupt is lower than or equal to a priority corresponding to the target task, continue to run the target task, where the target interrupt is one of the M interrupts. According to embodiments of this application, system performance and stability can be improved.

Inventors

• YU, Tianjun
• MALLORY, Adam
• HU, Xiameng

Assignees

• Huawei Technologies Co., Ltd.

Dates

Publication Date

20260513

Application Date

20240723

Claims (20)

1. A computing apparatus, wherein the computing apparatus comprises a scheduling module, an interrupt controller, and at least one processor core, wherein the scheduling module is configured to schedule N tasks, the interrupt controller is configured to schedule M interrupts, the N tasks and the M interrupts are marked by using unified priorities, one task corresponds to one priority, one interrupt corresponds to one priority, and M and N are integers greater than 0; and a target processor core in the at least one processor core is configured to: receive and run a target task sent by the scheduling module, wherein the target task is one of the N tasks; and receive a target interrupt sent by the interrupt controller, and if a priority corresponding to the target interrupt is lower than or equal to a priority corresponding to the target task, continue to run the target task, wherein the target interrupt is one of the M interrupts.
2. The computing apparatus according to claim 1, wherein the target processor core is further configured to: if the priority corresponding to the target interrupt is higher than the priority corresponding to the target task, suspend the target task and run the target interrupt.
3. The computing apparatus according to claim 1 or 2, wherein the scheduling module is further configured to: determine the target task from the N tasks, and determine, from the at least one processor core, the target processor core for the target task; and schedule the target task to the target processor core.
4. The computing apparatus according to any one of claims 1 to 3, wherein the target processor core comprises a priority register, and the target processor core is further configured to: configure the priority corresponding to the target task into the priority register.
5. The computing apparatus according to claim 4, wherein the target processor core is further configured to: when the target interrupt is received, compare the priority corresponding to the target interrupt with a priority currently stored in the priority register; and if the priority corresponding to the target interrupt is higher than the priority currently stored in the priority register, the priority corresponding to the target interrupt is higher than the priority corresponding to the target task; or if the priority corresponding to the target interrupt is lower than or equal to the priority currently stored in the priority register, the priority corresponding to the target interrupt is lower than or equal to the priority corresponding to the target task.
6. The computing apparatus according to claim 4 or 5, wherein the target processor core is specifically configured to: if the priority corresponding to the target interrupt is higher than the priority corresponding to the target task, update, to the priority register, the priority corresponding to the target interrupt; and suspend the target task and run the target interrupt.
7. The computing apparatus according to claim 6, wherein after the target processor runs the target interrupt, the target processor core is further configured to: restore the priority in the priority register to the priority corresponding to the target task, and continue to run the target task.
8. The computing apparatus according to any one of claims 4 to 7, wherein the target processor core is further configured to: when the target processor core runs an idle task, set the priority in the priority register to a lowest priority.
9. The computing apparatus according to any one of claims 4 to 8, wherein the target processor core is further configured to: when the target processor core runs the target interrupt, if an end-of-interrupt instruction is received, after retaining, within a preset time period, the priority corresponding to the target interrupt in the priority register, restore the priority in the priority register to the priority corresponding to the target task.
10. The computing apparatus according to any one of claims 4 to 9, wherein the target interrupt comprises indication information, and the indication information indicates the target processor core to run a first task, wherein a priority corresponding to the first task is higher than the priority corresponding to the target task, or a priority corresponding to the first task is lower than or equal to the priority corresponding to the target task, and the first task is one of the N tasks.
11. A task execution scheduling method, applied to a computing apparatus, wherein the computing apparatus comprises a scheduling module, an interrupt controller, and at least one processor core, wherein the scheduling module is configured to schedule N tasks, the interrupt controller is configured to schedule M interrupts, the N tasks and the M interrupts are marked by using unified priorities, one task corresponds to one priority, one interrupt corresponds to one priority, and M and N are integers greater than 0; and the method comprises: receiving and running, by using a target processor core in the at least one processor core, a target task sent by the scheduling module, wherein the target task is one of the N tasks; and receiving a target interrupt sent by the interrupt controller, and if a priority corresponding to the target interrupt is lower than or equal to a priority corresponding to the target task, continuing to run the target task, wherein the target interrupt is one of the M interrupts.
12. The method according to claim 11, wherein the method further comprises: if the priority corresponding to the target interrupt is higher than the priority corresponding to the target task, suspending, by using the target processor core, the target task, and running the target interrupt.
13. The method according to claim 11 or 12, wherein the method further comprises: determining, by using the scheduling module, the target task from the N tasks, and determining, from the at least one processor core, the target processor core for the target task; and scheduling the target task to the target processor core.
14. The method according to any one of claims 11 to 13, wherein the target processor core comprises a priority register, and the method further comprises: configuring, by using the target processor core, the priority corresponding to the target task into the priority register.
15. The method according to claim 14, wherein the method further comprises: when the target interrupt is received, comparing, by using the target processor core, the priority corresponding to the target interrupt with a priority currently stored in the priority register; and if the priority corresponding to the target interrupt is higher than the priority currently stored in the priority register, the priority corresponding to the target interrupt is higher than the priority corresponding to the target task; or if the priority corresponding to the target interrupt is lower than or equal to the priority currently stored in the priority register, the priority corresponding to the target interrupt is lower than or equal to the priority corresponding to the target task.
16. The method according to claim 14 or 15, wherein if the priority corresponding to the target interrupt is higher than the priority corresponding to the target task, suspending, by using the target processor core, the target task, and running the target interrupt comprise: if the priority corresponding to the target interrupt is higher than the priority corresponding to the target task, updating, to the priority register by using the target processor core, the priority corresponding to the target interrupt; and suspending, by using the target processor core, the target task, and running the target interrupt.
17. The method according to claim 16, wherein after the target processor runs the target interrupt, the method further comprises: restoring, by using the target processor core, the priority in the priority register to the priority corresponding to the target task, and continuing to run the target task.
18. The method according to any one of claims 14 to 17, wherein the method further comprises: when the target processor core runs an idle task, setting, by using the target processor core, the priority in the priority register to a lowest priority.
19. A computer storage medium, wherein the computer storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 11 to 18 is implemented.
20. A computer program product, wherein the computer program comprises instructions, and when the computer program is executed by a computer or a processor, the computer or the processor is enabled to perform the method according to any one of claims 11 to 18.

Description

This application claims priority to Chinese Patent Application No. 202311061280.2, filed with the China National Intellectual Property Administration on August 22, 2023 and entitled "COMPUTING APPARATUS AND RELATED TASK EXECUTION SCHEDULING METHOD", which is incorporated herein by reference in its entirety. TECHNICAL FIELD This application relates to the computer field, and in particular, to a computing apparatus and a related task execution scheduling method. BACKGROUND As complexity of systems and applications increases, requirements for system resource allocation, interrupt handling, latency, user experience, power consumption, and the like also arise. If an existing system is not optimized, interruptions and/or scheduling problems and the like occur in some scenarios, resulting in system performance degradation, for example, prolonged execution, additional kernel entry/exit overheads, reduced determinism, and increased power consumption. In terminal scenarios, problems such as stalling, high power consumption, and shortened standby time are also caused. In scenarios with high real-time requirements, time constraints may be missed, leading to system operation failures and poor system stability. For example, in autonomous driving scenarios, the system is interrupted by unnecessary interrupts, causing increased system overheads, greater impact on time constraints of tasks such as road condition perception and autonomous driving, and even task failures. Therefore, how to optimize the system is a current and future research direction. SUMMARY Embodiments of this application provide a computing apparatus and a related task execution scheduling method to improve system performance and stability. According to a first aspect, an embodiment of this application provides a computing apparatus. The computing apparatus includes a scheduling module, an interrupt controller, and at least one processor core. The scheduling module is configured to schedule N tasks. The interrupt controller is configured to schedule M interrupts. The N tasks and the M interrupts are marked by using unified priorities, one task corresponds to one priority, one interrupt corresponds to one priority, and M and N are integers greater than 0. A target processor core in the at least one processor core is configured to: receive and run a target task sent by the scheduling module, where the target task is one of the N tasks; and receive a target interrupt sent by the interrupt controller, and if a priority corresponding to the target interrupt is lower than or equal to a priority corresponding to the target task, continue to run the target task, where the target interrupt is one of the M interrupts. In this embodiment of this application, interrupts and tasks are marked by using unified priorities. If a priority corresponding to an interrupt is lower than or equal to the priority corresponding to the target task, the interrupt cannot interrupt the currently running task. The interrupt can interrupt the currently running task only when a unified priority corresponding to the interrupt is higher than the priority corresponding to the target task. In this way, integrity of running of a critical task is ensured. In the conventional technology, tasks and interrupts use independent priorities, and a priority of an interrupt is higher than a priority of any task by default. The interrupt can interrupt any running task, causing a problem that the interrupt unconditionally preempts a running critical task, and resulting in poor system stability. In this application, because tasks and interrupts are marked by using unified priorities, and only an interrupt with a priority higher than that of a task can interrupt the task, the interrupt does not arbitrarily interrupt a running critical task. In this way, a problem that an interrupt preempts any running task and prolongs an overall processing cycle of the critical task is resolved, and system performance and stability are improved. In some embodiments, the target processor core is further configured to: if the priority corresponding to the target interrupt is higher than the priority corresponding to the target task, suspend the target task and run the target interrupt. In this embodiment of this application, if the priority corresponding to the interrupt is higher than the priority corresponding to the target task, the interrupt may interrupt the currently running task, and then the target processor core may suspend the current task and run the interrupt, so that a computer system has a capability of responding to an emergency event, thereby improving working efficiency of the processor core. In some embodiments, the scheduling module is further configured to: determine the target task from the N tasks, and determine, from the at least one processor core, the target processor core for the target task; and schedule the target task to the target processor core. In this embodiment of this application, the sche