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EP-4742048-A1 - MEMORY PACKAGE INCLUDING PLURALITY OF STORAGE DEVICES

EP4742048A1EP 4742048 A1EP4742048 A1EP 4742048A1EP-4742048-A1

Abstract

A memory package includes a first storage device including a first controller configured to communicate with a host, and a second storage device including a second controller configured to communicate with the host, and perform a synchronization operation on the second storage device based on a synchronization signal received from the first controller. The first controller includes a first synchronizer configured to generate the synchronization signal based on a state of the first storage device, and a first pin electrically connected to the second controller. The second controller includes a second synchronizer configured to control the second controller to perform a synchronization operation based on the synchronization signal, and a second pin electrically connected to the first controller. The first synchronizer provides the synchronization signal to the second synchronizer via the first pin and the second pin.

Inventors

  • YANG, Seungyoon
  • KIM, EUNAH
  • YOO, Suhwa

Assignees

  • Samsung Electronics Co., Ltd.

Dates

Publication Date
20260513
Application Date
20251024

Claims (15)

  1. A memory package (10) comprising: a first storage device (100) comprising a first controller (110; 110a) configured to communicate with a host (20); and a second storage device (200) comprising a second controller (210; 210a) configured to communicate with the host (20), and perform a synchronization operation on the second storage device (200) based on a synchronization signal (SYNS1) received from the first controller (110; 110a), wherein the first controller (110; 110a) comprises: a first synchronizer (114; 114a) configured to generate the synchronization signal (SYNS1) based on a state of the first storage device (100), and a first pin (P1_1a) electrically connected to the second controller (210; 210a), wherein the second controller (210; 210a) comprises: a second synchronizer (214; 214a) configured to control the second controller (210; 210a) to perform the synchronization operation, based on the synchronization signal (SYNS1), and a second pin (P1_2a) electrically connected to the first controller (110; 110a), and wherein the first synchronizer (114; 114a) is configured to provide the synchronization signal (SYNS1) to the second synchronizer (214; 214a) via the first pin (P1_1a) and the second pin (P1_2a).
  2. The memory package (10) of claim 1, wherein each of the first storage device (100) and the second storage device (200) is configured to perform communication with the host (20) according to a universal flash storage (UFS) interface.
  3. The memory package (10) of claim 1 or 2, wherein the first controller (110) further comprises: a first receiving circuit (115_1) configured to form a plurality of first downstream lanes (DL1_1, DL2_1) with the host (20), and a first transmitting circuit (115_2) configured to form a plurality of first upstream lanes (UL1_1, UL2_1) with the host (20), and wherein the second controller (210) further comprises: a second receiving circuit (215_1) configured to form a plurality of second downstream lanes (DL1_2, DL2_2) with the host (20), and a second transmitting circuit (215_2) configured to form a plurality of second upstream lanes (UL1_2, UL2_2) with the host (20).
  4. The memory package (10) of claim 3, wherein a first number of lanes formed between the host (20) and the first controller (110) is the same as a second number of lanes formed between the host (20) and the second controller (210).
  5. The memory package (10) of any preceding claim, wherein the state of the first storage device (100) comprises a temperature of the first storage device (100), wherein the first synchronizer (114) is further configured to: monitor the state of the first storage device (100), generate the synchronization signal (SYNS1) based on identifying that the temperature of the first storage device (100) is greater than a reference value, and provide the synchronization signal (SYNS1) to the second controller (210), and wherein the second synchronizer (214) is further configured to control the second storage device (200) to operate in a throttling mode based on the synchronization signal (SYNS1).
  6. The memory package (10) of any preceding claim, wherein the state of the first storage device (100) comprises whether the first storage device (100) performs a garbage collection operation, wherein the first synchronizer (114) is further configured to: monitor the state of the first storage device (100), generate the synchronization signal (SYNS1) based on identifying that the first storage device (100) performs the garbage collection operation, and provide the synchronization signal (SYNS1) to the second controller (210), and wherein the second controller (210) is further configured to perform the garbage collection operation on the second storage device (200) based on the synchronization signal (SYNS1).
  7. The memory package (10) of any preceding claim, wherein the first controller (110; 110a) further comprises a third pin (P3_1a) electrically connected to the second controller (210; 210a), wherein the second controller (210; 210a) further comprises a fourth pin (P3_2a) electrically connected to the first controller (110; 110a), wherein the synchronization signal (SYNS1) constitutes a first synchronization signal (SYNS1), and wherein the first synchronizer (114; 114a) is further configured to: provide a second synchronization signal (SYNS3) to the second synchronizer (214; 214a) via the third pin (P3_1a) and the fourth pin (P3_2a).
  8. The memory package (10) of claim 7, wherein a second synchronization operation directed by the second synchronization signal (SYNS3) provided via the third pin (P3_1a) is different from the synchronization operation directed by the first synchronization signal (SYNS1) provided via the first pin (P1_1a).
  9. A memory package (10) comprising: a first storage device (100) comprising a first controller (110; 110c) configured to communicate with a host (20); and a second storage device (200) comprising a second controller (210; 210c) configured to communicate with the host (20), and perform a synchronization operation on the second storage device (200) based on a trigger signal (TRIG1) received from the first controller (110; 110c), wherein the first controller (110; 110c) comprises: a first synchronizer (114; 114c) configured to generate the trigger signal (TRIG1) based on a state of the first storage device (100), and a first trigger pin (P1_1c) and a first data pin (P3_1c) electrically connected to the second controller (210; 210c), wherein the second controller (210; 210c) comprises: a second synchronizer (214; 214c) configured to control the second controller (210; 210c) to perform the synchronization operation, based on the trigger signal (TRIG 1) and a data signal (DP1), and a second trigger pin (P1_2c) and a second data pin (P3_2c) electrically connected to the first controller (110; 110c), and wherein the first synchronizer (114; 114c) is further configured to: provide the trigger signal (TRIG1) to the second synchronizer (214; 214c) via the first trigger pin (P1_1c) and the second trigger pin (P1_2c), and provide the data signal (DP1) to the second synchronizer (214; 214c) via the first data pin (P3_1c) and the second data pin (P3_2c).
  10. The memory package (10) of claim 9, wherein the second synchronizer (214; 214c) is further configured to perform the synchronization operation corresponding to the data signal (DP1), based on receiving the trigger signal (TRIG1) and the data signal (DP1).
  11. The memory package (10) of claim 9 or 10, wherein the second synchronizer (214; 214c) is further configured to: perform a first synchronization operation based on the data signal (DP1) being a first value; stop the first synchronization operation based on the data signal (DP1) being a second value; perform a second synchronization operation based on the data signal (DP1) being a third value; and stop the second synchronization operation based on the data signal (DP1) being a fourth value.
  12. The memory package (10) of any one of claims 9 to 11, wherein the first controller (110c) further comprises a first clock signal pin (P5_1c) electrically connected to the second controller (210c), wherein the second controller (210c) further comprises a second clock signal pin (P5_2c) electrically connected to the first controller (110c), wherein the first controller (110c) further comprises a clock generator (118c) configured to generate a clock signal (CLK), and provide the clock signal (CLK) to the second controller (210c) via the first clock signal pin (P5_1c) and the second clock signal pin (P5_2c), and wherein the second controller (210c) is further configured to read a value represented by the data signal (DP1) based on the clock signal (CLK).
  13. The memory package (10) of any one of claims 9 to 12, wherein each of the first storage device (100) and the second storage device (200) is configured to perform communication with the host (20) according to a universal flash storage (UFS) interface.
  14. The memory package (10) of any one of claims 9 to 13, wherein the first controller (110; 110c) further comprises: a first receiving circuit (115_1) configured to form a plurality of first downstream lanes (DL1_1, DL2_1) with the host (20), and a first transmitting circuit (115_2) configured to form a plurality of first upstream lanes (UL1_1, UL2_1) with the host (20), and wherein the second controller (210; 210c) further comprises: a second receiving circuit (215_1) configured to form a plurality of second downstream lanes (DL1_2, DL2_2) with the host (20), and a second transmitting circuit (215_2) configured to form a plurality of second upstream lanes (UL1_2, UL2_2) with the host (20).
  15. The memory package (10) of any one of claims 9 to 14, wherein the state of the first storage device (100) comprises a temperature of the first storage device (100), wherein the first synchronizer (114; 114c) is further configured to: monitor the state of the first storage device (100), generate the trigger signal (TRIG1) and the data signal (DP1) based on identifying that the temperature of the first storage device (100) is greater than a reference value, and provide the trigger signal (TRIG1) and the data signal (DP1) to the second controller (210; 210c), and wherein the second synchronizer (214; 214c) is further configured to control the second storage device (200) to operate in a throttling mode in response to the trigger signal (TRIG1) and the data signal (DP1).

Description

FIELD The present disclosure relates to a memory package, and more particularly, to a memory package including a plurality of storage devices. BACKGROUND A universal flash storage (UFS) is a storage interface for supporting high-speed data transmission, and is widely used in compact electronic devices such as mobile devices. According to the UFS 4.0 Standard of the Joint Electron Device Engineering Council (JEDEC), which defines standard specifications for UFS devices, the connection between a host and the UFS device may be implemented in a 2-LANE manner. As artificial intelligence (AI) technology is rapidly developing, there is an increasing need to quickly process a large amount of data. In particular, as high transmission speed is required for learning AI models and real-time data processing, UFS systems communicating with hosts in a 2-LANE manner are experiencing limitations in meeting the data transmission requirement. Against the backdrop, a new technological approach is needed to further increase the data transmission speed between the host and the UFS storage. SUMMARY One or more embodiments provide a memory package including a plurality of universal flash storage (UFS) devices for increasing data transmission speed between a host and a memory package. Further, in one or more embodiments, operations of the plurality of UFS devices may be synchronized by transceiving synchronization signals between the plurality of UFS devices included in one memory package. By synchronizing the operations of the UFS devices, the temperature of the memory package may be efficiently managed. Further, in one or more embodiments, by synchronizing the operations of the UFS devices, the speed between a host and the plurality of UFS devices may be stably maintained. The issues addressed by embodiments are not limited to the above-mentioned issues, and other issues not mentioned may be clearly understood by one of ordinary skill in the art from the following descriptions. According to an aspect of the disclosure, there is provided a memory package including a first storage device including a first controller configured to communicate with a host, and a second storage device including a second controller configured to communicate with the host, and perform a synchronization operation on the second storage device based on a synchronization signal received from the first controller, wherein the first controller includes a first synchronizer configured to generate the synchronization signal based on a state of the first storage device, and a first pin electrically connected to the second controller, wherein the second controller includes a second synchronizer configured to control the second controller to perform a synchronization operation, based on the synchronization signal, and a second pin electrically connected to the first controller, and wherein the first synchronizer is configured to provide the synchronization signal to the second synchronizer via the first pin and the second pin. According to an aspect of the disclosure, there is provided a memory package including a first storage device including a first controller configured to communicate with a host, and a second storage device including a second controller configured to communicate with the host, and perform a synchronization operation on the second storage device based on a trigger signal received from the first controller, wherein the first controller includes a first synchronizer configured to generate the trigger signal based on a state of the first storage device, and a first trigger pin and a first data pin electrically connected to the second controller, wherein the second controller includes a second synchronizer configured to control the second controller to perform a synchronization operation, based on the trigger signal and the data signal, and a second trigger pin and a second data pin electrically connected to the first controller, and wherein the first synchronizer is further configured to provide the trigger signal to the second synchronizer via the first trigger pin and the second trigger pin, and provide the data signal to the second synchronizer via the first data pin and the second data pin. According to an aspect of the disclosure, there is provided a memory package including a first storage device including a first controller configured to communicate with a host, a second storage device including a second controller configured to communicate with the host, and perform a synchronization operation on the second storage device based on a synchronization signal received from the first controller, and a third storage device including a third controller configured to communicate with the host, and perform the synchronization operation on the third storage device based on the synchronization signal received from the first controller, wherein the first controller includes a first synchronizer configured to generate the synchronization signal based