EP-4742050-A1 - CIRCUITS AND METHODS FOR DIRECT MEMORY ACCESS USING A NETWORK-ON-CHIP

Abstract

A configurable integrated circuit includes a network-on-chip and a response buffer circuit coupled to the network-on-chip. The response buffer circuit includes a direct memory access circuit and a controller circuit. The direct memory access circuit generates read requests and write requests to access memory circuits. The controller circuit provides the read requests and the write requests to the memory circuits through the network-on-chip. The controller circuit exchanges data with the memory circuits for the read requests and the write requests.

Inventors

• Shirvaikar, Tara
• WEBER, SCOTT
• LOH, ZHI-HERN
• BLACKBURN, Jarrod
• HANSEN, IAN

Assignees

• Altera Corporation

Dates

Publication Date

20260513

Application Date

20251007

Claims (15)

1. A configurable integrated circuit comprising: a first network-on-chip; and a response buffer circuit coupled to the first network-on-chip wherein the response buffer circuit comprises a direct memory access circuit and a controller circuit, wherein the first network-on-chip is embedded in the configurable integrated circuit, wherein the direct memory access circuit generates first read requests and first write requests received from a host circuit to access first memory circuits, wherein the controller circuit provides the first read requests and the first write requests to the first memory circuits through the first network-on-chip, and wherein the controller circuit exchanges first data with the first memory circuits for the first read requests and the first write requests.
2. The configurable integrated circuit of claim 1, wherein the first memory circuits comprise block random access memory in the configurable integrated circuit.
3. The configurable integrated circuit of any one of claims 1-2, wherein the first memory circuits comprise memory external to the configurable integrated circuit in at least one die stacked vertically with the configurable integrated circuit.
4. The configurable integrated circuit of any one of claims 1-3, wherein the direct memory access circuit comprises a command first-in-first-out circuit that stores descriptors for read transactions and write transactions, and wherein the direct memory access circuit further comprises a finite state machine that uses the descriptors for the read transactions and the write transactions to generate the first read requests and the first write requests for the read transactions and for the write transactions.
5. The configurable integrated circuit of any one of claims 1-4, wherein the direct memory access circuit comprises a control status register circuit that stores status, error, pause, and reset information of read transactions and write transactions corresponding to the first read requests and the first write requests.
6. The configurable integrated circuit of claim 5, wherein the control status register circuit comprises a content addressable memory that stores a unique identifier, completion status, error type for any error, and an address of the error in each of the read transactions and the write transactions.
7. The configurable integrated circuit of any one of claims 1-6, wherein the direct memory access circuit comprises an error monitor circuit that polls incoming signals for errors in transactions that comprise the first read requests and the first write requests and forwards the errors to a storage circuit for storage.
8. The configurable integrated circuit of any one of claims 1-7 further comprising: a second network-on-chip coupled to the response buffer circuit, wherein the controller circuit provides second read requests and second write requests to second memory circuits through the second network-on-chip, and wherein the controller circuit exchanges second data with the second memory circuits for the second read requests and the second write requests.
9. The configurable integrated circuit of claim 8, wherein the second memory circuits comprise memory external to the configurable integrated circuit in at least one die peripheral to the configurable integrated circuit.
10. A method for performing read transactions and write transactions in a configurable integrated circuit, the method comprising: generating read requests and write requests for the read transactions and for the write transactions to access memory circuits using a direct memory access circuit in the configurable integrated circuit; using a scheduler circuit in the configurable integrated circuit to provide the read requests and the write requests from the direct memory access circuit to the memory circuits through a first network-on-chip in the configurable integrated circuit; and exchanging data with the memory circuits for the read requests and the write requests using the scheduler circuit.
11. The method of claim 10 further comprising: sending a response to a status query for one of the read or write transactions that comprises an error value, a tag to confirm that the response is for the one of the read or write transactions from the direct memory access circuit, a fill level of a command first-in-first-out circuit that stores descriptors for the read transactions and for the write transactions in the direct memory access circuit, or a completion status of the one of the read or write transactions through a second network-on-chip in the configurable integrated circuit from the direct memory access circuit.
12. The method of any one of claims 10-11, wherein the memory circuits are located in dies that are vertically stacked with the configurable integrated circuit, and wherein the read transactions and the write transactions are three dimensional transactions to and from the dies.
13. The method of any one of claims 10-12 further comprising: using a read identifier tracking mechanism to track one of the read transactions by tracking and mapping a returning read response to one of the read requests to allow a user to write to any addressable memory within a memory group.
14. The method of any one of claims 10-13, wherein generating the read requests and the write requests for the read transactions and for the write transactions further comprises: storing descriptors for the read transactions and the write transactions in a command first-in-first-out circuit in the direct memory access circuit, wherein the descriptors are configurable by a user to manipulate transaction synchronization, interleaving, and memory striding.
15. The method of any one of claims 10-14 further comprising: storing descriptors for the read transactions and the write transactions in a first-in-first-out circuit in the direct memory access circuit; and processing the descriptors to generate the read requests and the write requests for the read transactions and for the write transactions using a finite state machine in the direct memory access circuit.

Description

BACKGROUND Configurable integrated circuits (ICs) can be configured by users to implement desired custom logic functions. In a typical scenario, a logic designer uses computer-aided design (CAD) tools to design a custom circuit design. When the design process is complete, the computer-aided design tools generate an image containing configuration data bits. The configuration data bits are then loaded into configuration memory elements that configure configurable logic circuits in the integrated circuit to perform the functions of the custom circuit design. BRIEF DESCRIPTION OF DRAWINGS Figure 1 is a diagram that illustrates microarchitecture of a portion of an integrated circuit (IC) that includes a main network-on-chip (MNOC), a response buffer circuit including a direct memory access (DMA) circuit, and a micro-network-on-chip (uNOC).Figure 2A is a diagram that illustrates an example of a status query performed by a host by sending a read request with an initial write request and write data to a response buffer circuit.Figure 2B is a diagram that illustrates an example of a status query performed by a host using a push/push write request to a localized mailbox.Figure 3 is a diagram that illustrates an example of a system where a host is sending a descriptor to the DMA circuit of Figure 1, then sending a status request on that transaction, and finally receiving a status response.Figure 4 is a diagram that illustrates examples of states of a finite state machine (FSM) in the FSM circuit of Figure 1 and transitions between the states.Figure 5 is a diagram that illustrates components in a fabric sector of an integrated circuit (IC) that can implement read and write transactions to memory.Figure 6 is a diagram that illustrates an example of a system that can be used for a two-dimensional (2D) read or write application.Figure 7 is a diagram that illustrates an example of a system that can be used for a three-dimensional (3D) read or write application.Figure 8 is a diagram of an illustrative example of a configurable integrated circuit (IC).Figure 9A illustrates a block diagram of a system that can be used to implement a circuit design to be programmed into a programmable logic device using design software.Figure 9B is a diagram that depicts an example of a programmable logic device that includes fabric dies and base dies that are coupled to one another via microbumps.Figure 10 is a block diagram illustrating a computing system configured to implement one or more aspects of the embodiments described herein. DETAILED DESCRIPTION In some types of previously known configurable integrated circuits (ICs), such as field programmable gate arrays (FPGAs), direct and remote proxy transactions to memory circuits in the ICs were initiated by external hosts. This technique did not allow for strided memory access or indirection, was not optimized for use cases that take advantage of a central scheduler, and was not optimized for three dimensional (3D) use cases. According to some examples disclosed herein, a DMA (Direct Memory Access) circuit in a response buffer (RB) circuit in an integrated circuit (IC) performs efficient access to memory circuit blocks by controlling transactions all over the IC (e.g., within a fabric region of the IC) by emphasizing transaction indirection. The response buffer circuit is coupled to a micro-Network-On-Chip (micro-NOC). The DMA circuit enhances overall system efficiency and throughput by enabling a central scheduler (or multiple schedulers) to control transactions all over the IC. The DMA enables artificial intelligence (AI) use cases, more direct communication with three-dimensional (3D) memories, and communication with block random access memory (BRAM) embedded data in the IC. According to some examples, the DMA circuit can also include a finite state machine (FSM) that unrolls a received descriptor that includes a read or write request to be sent out, a control status register (CSR) circuit including a content addressable memory (CAM) that keeps track of outstanding transactions, and an error monitoring circuit block that constantly polls for returning error signals. Each transaction can be a read or write transaction. Each read transaction and each write transaction can include one or more read requests and/or write requests, as disclosed below. The DMA circuit also includes key striding and transaction control capabilities. In addition, the DMA circuit can update a mailbox (e.g., that is local to a host), after the transaction is complete. The DMA circuit has the advantage of having indirection that allows a user to efficiently access all of the embedded BRAM in the IC and external 3D memory ICs that are in communication with the IC along the micro-network-on-chip (uNOC). Being local to the host, the mailbox minimizes the latency initially required for the host to poll for completion, increasing overall transactional efficiency. The DMA circuit is also highly configurable, allowing the