EP-4742051-A1 - MEMORY MODULE, ELECTRONIC DEVICE AND SIGNAL TRANSMISSION METHOD

EP4742051A1EP 4742051 A1EP4742051 A1EP 4742051A1EP-4742051-A1

Abstract

A memory module, an electronic device, and a signal transmission method are provided. The memory module is a dual in-line memory module. A foolproof bayonet and a locking bayonet are disposed on a circuit board of the memory module, and a plurality of memory chips are separately disposed on board surfaces on two sides of the circuit board. The plurality of memory chips are connected to a processing chip through a parallel bus, and the processing chip is connected to a gold finger interface through a serial bus. Through this arrangement, the memory module can implement a serial interconnection relationship by using a connector, so that a data transmission rate can be reliably improved, crosstalk and simultaneous switching noise that are generated because high-speed transmission is performed based on the parallel bus can be avoided, and SI can be effectively improved. The memory module actually occupies a small board area, which is conducive to a high-density layout. In general, this provides technical assurance for a high-density layout and high-performance running of an architecture. In addition, the memory module occupies roughly same physical space as a conventional memory module, which is conducive to a standardized design of a structure of a mainboard.

Inventors

WANG, Luo
LUO, FEI
WANG, GUOYU

Assignees

Huawei Technologies Co., Ltd.

Dates

Publication Date: 20260513
Application Date: 20240311

Claims (16)

A memory module, wherein the memory module is a dual in-line memory module, comprising: a circuit board, wherein a foolproof bayonet and a locking bayonet are disposed on the circuit board; a processing chip and a plurality of memory chips disposed on the circuit board; and a gold finger interface located at an edge of the circuit board, wherein the plurality of memory chips are connected to the processing chip through a parallel bus, and the processing chip is connected to the gold finger interface through a serial bus.
The memory module according to claim 1, wherein the gold finger interface comprises a first power supply pin region, a second power supply pin region, a management and control signal pin region, and a serial bus pin region that are separately disposed on board surfaces on two sides of the circuit board, the first power supply pin region is configured to provide a first voltage power supply, the second power supply pin region is configured to provide a second voltage power supply, and a voltage of the second voltage power supply is lower than a voltage of the first voltage power supply; and each of the board surfaces on the two sides of the circuit board comprises two serial bus pin regions; and in an arrangement direction of the gold finger interface, the first power supply pin region is located at one end of the circuit board, one of the two serial bus pin regions is arranged adjacent to the first power supply pin region, the other of the two serial bus pin regions is located at the other end of the circuit board, and the management and control signal pin region and the second power supply pin region are located between the two serial bus pin regions.
The memory module according to claim 2, wherein a blank pin is disposed between the first power supply pin region and the adjacently arranged serial bus pin region.
The memory module according to claim 3, wherein the gold finger interface further comprises a differential clock pin, and the differential clock pin is located between the blank pin and the serial bus pin region arranged adjacent to the first power supply pin region.
The memory module according to any one of claims 2 to 4, wherein the serial bus pin region comprises differential pair pins that are spaced apart, the differential pair pin comprises two differential signal pins configured to transmit a differential signal, a ground pin is disposed between two adjacent differential pair pins, parts that are of the gold finger interface and that are located on a board surface on one side of the circuit board are gold fingers on a first surface, and parts that are of the gold finger interface and that are located on a board surface on the other side of the circuit board are gold fingers on a second surface.
The memory module according to claim 5, wherein the serial bus pin region comprises eight differential pair pins that are spaced apart, and differential pair pins of the gold fingers on the first surface and differential pair pins of the gold fingers on the second surface are staggered.
The memory module according to claim 6, wherein four ground pins are disposed between adjacent differential pair pins, and in the arrangement direction of the gold finger interface, four ground pins on gold fingers on one surface from the gold fingers on the first surface and the gold fingers on the second surface are consecutively arranged by using one differential pair pin on gold fingers on the other surface from the gold fingers on the first surface and the gold fingers on the second surface as a center.
The memory module according to claim 7, wherein four ground pins on one side of the gold fingers on the first surface are connected through a first conductor sheet, t four ground pins on one side of the gold fingers on the second surface are connected through a second conductor sheet, the first conductor sheet is electrically connected to four third pads, the second conductor sheet is electrically connected to four fourth pads, the third pads on the one side of the gold fingers on the first surface are in a one-to-one correspondence with the fourth pads on the one side of the gold fingers on the second surface, and the third pad and the fourth pad that correspond to each other on the two sides are formed through one via.
The memory module according to claim 6, wherein two ground pins are disposed between adjacent differential pair pins, a differential pair pin on one side of the gold fingers on the first surface is arranged in correspondence with two ground pins on one side of the gold fingers on the second surface, and the differential pair pin on the one side of the gold fingers on the second surface is arranged in correspondence with two ground pins on the one side of the gold fingers on the first surface.
The memory module according to claim 9, wherein the two ground pins on the one side of the gold fingers on the first surface are connected through a first conductor sheet, the two ground pins on the one side of the gold fingers on the second surface are connected through a second conductor sheet, the first conductor sheet is electrically connected to three third pads, the second conductor sheet is electrically connected to three fourth pads, two third pads located on two edge sides and electrically connected to the first conductor sheet are in a one-to-one correspondence with fourth pads located on two edge sides and electrically connected to the second conductor sheet, and the third pad and the fourth pad that correspond to each other on the two sides are formed through one via.
The memory module according to claim 6, wherein one ground pin is disposed between adjacent differential pair pins.
The memory module according to claim 11, wherein the ground pin on one side of the gold fingers on the first surface is connected to a first conductor sheet, the first conductor sheet is electrically connected to two third pads, the ground pin on one side of the gold fingers on the second surface is connected to a second conductor sheet, the second conductor sheet is electrically connected to two fourth pads, the third pads on the one side of the gold fingers on the first surface are in a one-to-one correspondence with the fourth pads on the one side of the gold fingers on the second surface, and the third pad and the fourth pad that correspond to each other on the two sides are formed through one via.
The memory module according to any one of claims 1 to 12, wherein the memory module is a memory expansion card, several memory chips are disposed on the circuit board, and the processing chip is a memory expansion chip configured to manage and control the several memory chips.
An electronic device, comprising a housing and a mainboard and a memory module that are disposed in the housing, wherein a DIMM connector is disposed on the mainboard, the memory module is inserted into the DIMM connector on the mainboard, and the memory module is the memory module according to any one of claims 1 to 13.
A signal transmission method, wherein the signal transmission method is applied to a memory module, the memory module is a dual in-line memory module, the memory module comprises a circuit board, a processing chip, a plurality of memory chips, and a gold finger interface, a foolproof bayonet and a locking bayonet are disposed on the circuit board, the processing chip and the plurality of memory chips are disposed on the circuit board, the gold finger interface is located at an edge of the circuit board, the plurality of memory chips are connected to the processing chip through a parallel bus, and the processing chip is connected to the gold finger interface through a serial bus; and the method comprises the following step: transmitting a data signal, a control signal, and a power supply signal through the gold finger interface.
The signal transmission method according to claim 15, wherein the gold finger interface comprises a first power supply pin region, a second power supply pin region, a serial bus pin region, and a management and control signal pin region that are separately disposed on board surfaces on two sides of the circuit board, the first power supply pin region is configured to provide a first voltage power supply, the second power supply pin region is configured to provide a second voltage power supply, and a voltage of the second voltage power supply is lower than a voltage of the first voltage power supply; each of the board surfaces on the two sides of the circuit board comprises two serial bus pin regions; and in an arrangement direction of the gold finger interface, the first power supply pin region is located at one end of the circuit board, one of the two serial bus pin regions is arranged adjacent to the first power supply pin region, the other of the two serial bus pin regions is located at the other end of the circuit board, and the management and control signal pin region and the second power supply pin region are located between the two serial bus pin regions; and transmitting the data signal, the control signal, and the power supply signal through the gold finger interface comprises: transmitting the data signal by using the serial bus pin region, transmitting the control signal by using the management and control signal pin region, transmitting a first power supply signal in the power supply signal by using the first power supply pin region, and transmitting a second power supply signal in the power supply signal by using the second power supply pin region.

Description

This application claims priority to Chinese Patent Application No. 202310937615.6, filed with the China National Intellectual Property Administration on July 27, 2023 and entitled "MEMORY MODULE, ELECTRONIC DEVICE, AND SIGNAL TRANSMISSION METHOD", which is incorporated herein by reference in its entirety. TECHNICAL FIELD Embodiments of this application relate to the field of computer hardware, and in particular, to a memory module, an electronic device, and a signal transmission method. BACKGROUND A dual in-line memory module (dual in-line memory module, DIMM) connector is used in a double data rate (double data rate, DDR) parallel bus system. The DIMM connector is installed and connected to a memory module, to implement connection between a central processing unit (central processing unit, CPU) and a synchronous dynamic random access memory (synchronous dynamic random access memory, SDRAM) chip configured on the memory module. Through this connection, an efficient and low-cost memory system is formed between the CPU and a storage medium, to implement a fast read/write access operation. With development of data-intensive application such as high-performance computing and artificial intelligence, requirements for bandwidth and a capacity of the memory system continuously increase, and this prompts continuous improvement in a DDR parallel bus rate and an SDRAM chip capacity on the memory module. Currently, a DDR parallel bus has gradually transitioned from a DDR fourth generation (DDR4) to a DDR fifth generation (DDR5), and a single-line rate has also increased from 2.133 Gbps-3.2 Gbps to 4.8 Gbps-8.4 Gbps. Due to problems such as crosstalk and simultaneous switching noise (Simultaneous Switching Noise, SSN), further improving the single-line rate will affect signal integrity (SI). To resolve problems of the bandwidth and the capacity of the memory system, a serial memory solution is proposed in the industry to implement memory expansion. A memory expansion module and a mainboard may be connected in different manners. A typical manner is using a GENZ (Generation Z, which is a high-speed protocol) connector for vertical insertion. A height size of the GENZ connector is large, and is limited by internal space of a device. Consequently, a board surface width of the memory expansion module cannot meet a layout requirement of a large-size expansion chip. Another typical manner is using a GENZ straddle mount connector for horizontal insertion. The memory expansion module is arranged in parallel with the mainboard, and occupies large space on a board surface of the mainboard, which is not conducive to high-density implementation of an architecture. SUMMARY Embodiments of this application provide a memory module, an electronic device, and a signal transmission method, to provide technical assurance for improving SI and considering a design requirement of a high-density layout of an architecture while effectively improving a signal transmission rate. A first aspect of embodiments of this application provides a memory module. The memory module includes a circuit board, a processing chip and a plurality of memory chips disposed on the circuit board, and a gold finger interface located at an edge of the circuit board. A foolproof bayonet and a locking bayonet are disposed on the circuit board, and a plurality of memory chips are separately disposed on board surfaces on two sides of the circuit board. The plurality of memory chips are connected to the processing chip through a parallel bus, and the processing chip is connected to the gold finger interface through a serial bus. Through this arrangement, the memory module can implement a serial interconnection relationship by using a connector. A data transmission rate can be reliably improved by using the serial bus, and crosstalk and simultaneous switching noise that are generated because high-speed transmission is performed based on the parallel bus can be avoided to some extent, so that reliability and stability requirements of signal transmission are met, and SI is effectively improved. In addition, based on a small height size of a DIMM connector, for same assembly space, the circuit board provided in this solution has a large board surface width, so that a layout of a large component can be implemented. In addition, the memory module is in a vertical insertion manner, and actually occupies a small board area. In general, this provides technical assurance for a high-density layout and high-performance running of an architecture. In addition, physical space occupied by the memory module in an electronic device is roughly the same as physical space occupied by a conventional memory module, which is conducive to a standardized design of a structure of a mainboard of the electronic device, and can further improve structural adaptability between the memory module and the mainboard. For example, the memory module may be a memory expansion card, and the processing chip is a