EP-4742079-A1 - RESYNTHESIS FOR POST-MAPPING OPTIMIZATION

EP4742079A1EP 4742079 A1EP4742079 A1EP 4742079A1EP-4742079-A1

Abstract

The present technology includes a resynthesis engine for improving digital circuits' power, performance, and area (PPA). The resynthesis engine operates directly on a mapped netlist space. The resynthesis engine replaces subnetworks with low-cost structures from a database, which can be updated dynamically during optimization. The resynthesis engine can efficiently optimize for various objectives, including area, delay, and dynamic power. The resynthesis engine is also capable of significantly reducing glitching, which contributes to power consumption in arithmetic circuits.

Inventors

RUIC, Dino
XU, XIAOQING
COSTAMAGNA, Andrea

Assignees

GDM Holding LLC

Dates

Publication Date: 20260513
Application Date: 20251021

Claims (15)

A computer-implemented method of resynthesis, the method comprising: identifying, by at least one processor, at least one cut within a netlist; obtaining, by the at least one processor, at least one sub-circuit from a dynamic database, wherein the at least one sub-circuit performs a same function as the at least one cut; determining, by the at least one processor, a first cost value for the at least one cut based on a cost function; determining, by the at least one processor, a second cost value for the at least one sub-circuit based on the cost function; replacing, by the at least one processor, the at least one cut with the at least one sub-circuit in the netlist when the first cost value is larger than the second cost value; and replacing, by the at least one processor, the at least one sub-circuit with the at least one cut in the dynamic database when the second cost value is larger than the first cost value.
The method of claim 1, wherein the cut is a supercell comprising a combination of multiple cells from a standard cell library.
The method of claim 2, wherein the supercell includes at least one cell that is a multi-output cell.
The method of any one of claims 1 to 3, wherein identifying the at least one cut within the netlist comprises: a) extracting a sub-network of nodes within the netlist based on a target node; and identifying the at least one cut within a window; and optionally: b) identifying a set of nodes between the target node and inputs to the at least one cut; and expanding the set of nodes to include additional nodes with fan-ins contained within the set of nodes.
The method of any one of claims 1 to 4, wherein identifying the at least one cut within the netlist comprises: performing a window simulation to identify a dependency cut as the at least one cut.
The method of any one of claims 1 to 5, wherein determining the first cost value for the at least one cut comprises: operating a multi-objective function that optimizes at least one of metric selected from a group comprising area, timing, power, toggle activity, or glitching.
The method of any one of claims 1 to 6, wherein the dynamic database comprises respective keys for corresponding stored sub-circuits, wherein each of the respective keys is based on a truth table of the corresponding stored sub-circuits, wherein obtaining the at least one sub-circuit from the dynamic database comprises: generating a key based on a binary representation of a truth table of the at least one cut; and querying the dynamic database using the key to obtain the at least one sub-circuit.
The method of any one of claims 1 to 7, wherein the cost function includes an evaluation of dynamic switching activity within the netlist.
The method of any one of claims 1 to 8, further comprising: determining, using heuristic filtering, whether substituting the at least one cut with the at least one sub-circuit violates at least one design constraint of the netlist; and/or performing design-space exploration by dynamically adjusting one or more optimization parameters toward minimizing a specified metric; and/or operating a machine learning model to learn a performance metric to be used for evaluating the first cost value and the second cost value.
A computing system, comprising: at least one memory device configured to store instructions for performing resynthesis during electronic design automation; and at least one processor connected to the at least one memory device, wherein the at least one processor is configured to execute the instructions to: identify at least one cut within a netlist; obtain at least one sub-circuit from a dynamic database, wherein the at least one sub-circuit performs a same function as the at least one cut; determine a first cost value for the at least one cut based on a cost function; determine a second cost value for the at least one sub-circuit based on the cost function; replace the at least one cut with the at least one sub-circuit in the netlist when the first cost value is larger than the second cost value; and replace the at least one sub-circuit with the at least one cut in the dynamic database when the second cost value is larger than the first cost value.
The system of claim 10, wherein the identification of the at least one cut within the netlist comprises: a) perform a window simulation to identify a dependency cut as the at least one cut; and/or b) extract a sub-network of nodes within the netlist based on a target node; and identify the at least one cut within a window, and wherein the identification of the at least one cut within the window comprises: identify a set of nodes between the target node and inputs to the at least one cut; and expand the set of nodes to include additional nodes with fan-ins contained within the set of nodes.
The system of claim 10 or 11, wherein the determinations of the first cost value for the at least one cut comprises: operate a multi-objective function that optimizes at least one of metric selected from a group comprising area, timing, power, toggle activity, or glitching.
The system of any one of claims 10 to 12, wherein the dynamic database comprises respective keys for corresponding stored sub-circuits, wherein each of the respective keys is based on a truth table of the corresponding stored sub-circuits, wherein obtaining the at least one sub-circuit from the dynamic database comprises: generate a key based on a binary representation of a truth table of the at least one cut; and query the dynamic database using the key to obtain the at least one sub-circuit.
The system of any one of claims 10 to 13, wherein the cost function includes an evaluation of dynamic switching activity within the netlist.
The system of any one of claims 10 to 14, wherein the at least one processor is configured to execute the instructions to: determine, using heuristic filtering, whether substituting the at least one cut with the at least one sub-circuit violates at least one design constraint of the netlist; and/or operate a machine learning model to learn a performance metric to be used for evaluating the first cost value and the second cost value; and/or perform design-space exploration by dynamically adjusting one or more optimization parameters toward minimizing a specified metric.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. Provisional Application No. 63/719,148, filed November 12, 2024, the entire disclosure of which is incorporated herein by reference. BACKGROUND Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD), refers to a process, and set of software tools, used for designing electronic systems, such as integrated circuits (ICs), printed circuit boards (PCBs), and the like. The EDA process encompasses a series of steps to design and implement digital circuits from high-level specifications to physical hardware. Some steps in the EDA process include logic synthesis and physical design. Logic synthesis is a process of converting an abstract specification of circuit behavior into a circuit design implementation in terms of logic gates. This involves transforming the abstract specification, such as a register-transfer level (RTL) description, into a network of logic gates, such as a logic gate-level netlist, that can be physically implemented on an IC. The logic synthesis process also includes logic optimization and technology mapping. Logic optimization involves optimizing the netlist based on design constraints and objectives, such as timing constraints and specific target implementation technology. Logic mapping involves selecting logical elements to implement the optimized netlist. Objectives of the optimization process may include optimization of timing, area, and power of the resultant design. However, since accurate metrics, such as power, performance, and area (PPA) metrics, are only available after technology mapping is done, a common practice is to use proxy metrics to estimate the timing, area, and power metrics during logic optimization. For example, the node count of a netlist is often used to approximate the design area and the level count of the netlist is often used to approximate maximum delay. However, the correlation between level count and the maximum delay is not ideal or necessarily accurate. Therefore, using such proxy metrics during logical optimization may not yield the most optimal circuit designs in terms of, for example, PPA. Thus, such approaches can result in insufficient and/or ineffective solutions. SUMMARY The present technology is related to a versatile resynthesis engine capable of optimizing circuits after technology mapping for various objectives, including area, delay, and dynamic power. Thus, the technology provides resynthesis for post-mapping optimization. Some embodiments include a computer-implemented method of resynthesis. The method includes identifying, by at least one processor, at least one cut within a netlist. The method includes obtaining, by the at least one processor, at least one sub-circuit from a dynamic database, wherein the at least one sub-circuit performs a same function as the at least one cut. The method includes determining, by the at least one processor, a first cost value for the at least one cut based on a cost function. The method includes determining, by the at least one processor, a second cost value for the at least one sub-circuit based on the cost function. The method includes replacing, by the at least one processor, the at least one cut with the at least one sub-circuit in the netlist when the first cost value is larger than the second cost value. The method includes replacing, by the at least one processor, the at least one sub-circuit with the at least one cut in the dynamic database when the second cost value is larger than the first cost value. In some embodiments, the cut is a supercell comprising a combination of multiple cells from a standard cell library. In some embodiments, the supercell includes at least one cell that is a multi-output cell. In some embodiments, the supercell is a multi-output supercell. In some embodiments, the at least one cut is a structural cut, a non-structural cut, or a dependency cut. In some embodiments, identifying the at least one cut within the netlist comprises: extracting a sub-network of nodes within the netlist based on a target node; and identifying the at least one cut within a window. In some embodiments, identifying the at least one cut within the window comprises: identifying a set of nodes between the target node and inputs to the at least one cut; and expanding the set of nodes to include additional nodes with fan-ins contained within the set of nodes. In some embodiments, identifying the at least one cut within the netlist comprises: performing a window simulation to identify a dependency cut as the at least one cut. In some embodiments, determining the first cost value and/or determining the second cost value comprises: operating a multi-objective function that optimizes at least one of metric selected from a group comprising area, timing, power, toggle activity, or glitching. In some embodiments, the dynamic database comprises respective keys for correspondi