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EP-4742081-A1 - FRONT-END-OF-LINE FLOORPLAN OF INTEGRATED CIRCUIT THAT HAS DUMMIES INSERTED BY BLOCKAGE-AIDED DUMMY INSERTION AND RELATED METHOD

EP4742081A1EP 4742081 A1EP4742081 A1EP 4742081A1EP-4742081-A1

Abstract

A front-end-of-line, FEOL, floorplan (200) of an integrated circuit includes a plurality of FEOL components (202, 204, 206, 208), a non-rectangle-shaped empty region, a first FEOL dummy (218), and a second FEOL dummy (216). The non-rectangle-shaped empty region is located between the FEOL components (202, 204, 206, 208), and includes a first empty region (212) in a first direction and a second empty region (210) in a second direction perpendicular to the first direction, where the first empty region (212) has a first end connected to the second empty region (210). The first FEOL dummy (218) is inserted in the first empty region (212). The second FEOL dummy (216) is inserted in the second empty region (210). The first FEOL dummy (218) is separated from the second FEOL dummy (216) at the first end of the first empty region (212).

Inventors

  • TSAI, YI-CHUN
  • HUANG, SHAO-HUA
  • HSU, WEI-MIN
  • CHANG, CHI-HSIN
  • SIM, Vanessa Kim Ann
  • LIN, SHIH-YUN
  • DIA, KIN HOOI
  • YANG, JEN-HANG
  • PUA, Siaw Fuang
  • CHIU, YI-TE
  • GUO, YI
  • LIU, Hsu-Hua
  • ZHANG, SHUYUAN
  • CHENG, Chieh-Jou
  • WONG, Kian Loo
  • CHANG, YI-PING
  • CHEN, YI-JUNG
  • CHEN, SZU-YING

Assignees

  • MEDIATEK INC.

Dates

Publication Date
20260513
Application Date
20251106

Claims (15)

  1. A front-end-of-line, FEOL, floorplan (200, 300) of an integrated circuit characterized by : a plurality of FEOL components (202, 204, 206, 208, 302, 304, 306, 308); a non-rectangle-shaped empty region, located between the plurality of FEOL components (202, 204, 206, 208, 302, 304, 306, 308), wherein the non-rectangle shaped empty region comprises: a first empty region (212, 310), in a first direction; and a second empty region (210, 312), in a second direction perpendicular to the first direction, wherein the first empty region (212, 310) has a first end connected to the second empty region (210, 312); a first FEOL dummy (218, 316), inserted in the first empty region (212, 310); and a second FEOL dummy (216, 318), inserted in the second empty region (210, 312), wherein the first FEOL dummy (218, 316) is separated from the second FEOL dummy (216, 318) at the first end of the first empty region (212, 310).
  2. The FEOL floorplan (200, 300) of claim 1, characterized in that the first empty region (212, 310) has a minimum width specified by design rules of a semiconductor foundry, or the second empty region (210, 312) has a minimum width specified by design rules of a semiconductor foundry.
  3. The FEOL floorplan (200, 300) of any one of claims 1 or 2, characterized in that the second empty region (210, 312) has a minimum width specified by design rules of a semiconductor foundry.
  4. The FEOL floorplan (200, 300) of any one of claims 1 to 3, characterized in that the first FEOL dummy (218, 316) is separated from the second FEOL dummy (216, 318) by an FEOL blockage (222, 322) defined at the first end of the first empty region (212, 310).
  5. The FEOL floorplan (200, 300) of any one of claims 1 to 4, characterized in that the non-rectangle shaped empty region further comprises: a third empty region (214, 314), in the first direction, wherein the third empty region (214, 314) has a first end connected to the second empty region (210, 312); and the FEOL floorplan (200, 300) further comprises: a third FEOL dummy (220, 320), inserted in the third empty region (214, 314), wherein the third FEOL dummy (220, 320) is separated from the second FEOL dummy (216, 318) at the first end of the third empty region (214, 314).
  6. The FEOL floorplan (200, 300) of any one of claims 1 to 5, characterized in that the first FEOL dummy (218, 316) is an oxide diffusion dummy, a poly dummy, or a Cut Poly dummy; or wherein the second FEOL dummy (216, 318) is an oxide diffusion dummy, a poly dummy, or a Cut Poly dummy.
  7. The FEOL floorplan (200, 300) of any one of claims 1 to 6, characterized in that the first direction is a horizontal direction of the FEOL floorplan (200, 300), and the second direction is a vertical direction of the FEOL floorplan (200, 300).
  8. The FEOL floorplan (200, 300) of any one of claims 1 to 7, characterized in that the first direction is a vertical direction of the FEOL floorplan (200, 300), and the second direction is a horizontal direction of the FEOL floorplan (200, 300).
  9. A method of designing a front-end-of-line, FEOL, floorplan (200, 300) of an integrated circuit characterized by : defining a plurality of FEOL components (202, 204, 206, 208, 302, 304, 306, 308) in the FEOL floorplan (200, 300), wherein a non-rectangle-shaped empty region is located between the plurality of FEOL components (202, 204, 206, 208, 302, 304, 306, 308), and comprises: a first empty region (212, 310), in a first direction; and a second empty region (210, 312), in a second direction perpendicular to the first direction, wherein the first empty region (212, 310) has a first end connected to the second empty region (210, 312); defining a first FEOL blockage (222, 322) at the first end of the first empty region (212, 310); and running a dummy insertion utility to automatically insert a first FEOL dummy (218, 316) and a second FEOL dummy (216, 318), wherein the first FEOL blockage (222, 322) assists the dummy insertion utility in inserting the first FEOL dummy (218, 316) in the first empty region (212, 310) only.
  10. The method of claim 9, characterized in that the first empty region (212, 310) has a minimum width specified by design rules of a semiconductor foundry.
  11. The method of any one of claims 9 or 10, characterized in that the second empty region (210, 312) has a minimum width specified by design rules of a semiconductor foundry.
  12. The method of any one of claims 9 to 11, characterized in that the non-rectangle shaped empty region further comprises: a third empty region (214, 314), in the first direction, wherein the third empty region (214, 314) has a first end connected to the second empty region (210, 312); and the method further comprises: defining a second FEOL blockage (224, 324) at the first end of the third empty region (214, 314); and running the dummy insertion utility to automatically insert a third FEOL dummy (220, 320), wherein the second FEOL blockage (224, 324) assists the dummy insertion utility in inserting the third FEOL dummy (220, 320) in the third empty region (214, 314) only.
  13. The method of any one of claims 9 to 12, characterized in that the first FEOL dummy (218, 316) is an oxide diffusion dummy, a poly dummy, or a Cut Poly dummy; or wherein the second FEOL dummy (216, 318) is an oxide diffusion dummy, a poly dummy, or a Cut Poly dummy.
  14. The method of any one of claims 9 to 13, characterized in that the first direction is a horizontal direction of the FEOL floorplan (200, 300), and the second direction is a vertical direction of the FEOL floorplan (200, 300).
  15. The method of any one of claims 9 to 14, characterized in that the first direction is a vertical direction of the FEOL floorplan (200, 300), and the second direction is a horizontal direction of the FEOL floorplan (200, 300).

Description

Field of the Invention The present invention relates to an integrated circuit (IC) design, and more particularly, to a front-end-of-line (FEOL) floorplan of an IC that has FEOL dummies inserted by blockage-aided FEOL dummy insertion and a related method. Background of the Invention IC fabrication is a complex semiconductor process during which electronic circuits are created in and on a wafer. The semiconductor process is a multiple-step sequence which can be divided into two major processing stages, namely an FEOL process and a back-end-of-line (BEOL) process. The FEOL process refers to the construction of the components (e.g., transistors) of the IC directly inside the wafer. Specifically, the FEOL process focuses on forming electronic device structures that define IC's basic functions. Since the FEOL process is the first stage of the semiconductor process, it sets the foundation for the subsequent stages, including the BEOL process. Specifically, once all the components of the IC are ready, the BEOL process is performed to deposit the metal wiring between the individual components in order to interconnect them. After the BEOL process, a back-end process (also called post-fab process) is performed, which includes wafer testing, die separation, die testing, IC packaging, and final testing. An FEOL floorplan of an IC includes a plurality of FEOL components. For example, an FEOL component may be a macro, a static random access memory (SRAM), an intellectual property (IP) cell, or a standard cell region. It is possible that FEOL components with different dimensions (e.g., different widths and/or different heights) may be included in the FEOL floorplan, resulting in a non-rectangle shaped empty region (e.g., a Z-shaped empty region) between non-identical FEOL components. When the non-rectangle shaped empty region has a minimum horizontal/vertical width specified by design rules of a semiconductor foundry, a dummy insertion utility provided by the semiconductor foundry has dummy insertion utility limitations, and may have difficult in inserting horizontal/vertical dummies into the non-rectangle shaped empty region. In other words, dummy insertion cannot work in the non-rectangle shaped empty region with minimum spacing, which causes design rule checking (DRC) violation. One conventional approach is to redo the FEOL floorplan to enlarge the empty region for accommodating FEOL dummies inserted by the dummy insertion utility provided by the semiconductor foundry. After the designer enlarges the empty region by redoing the FEOL floorplan, he/she needs to redo placement, clock tree synthesis (CTS), routing, and physical verification (PV) again. As a result, the conventional approach increases the die area as well as the time to market. Summary of the Invention This in mind, the present invention aims at providing an FEOL floorplan of an IC that has a non-rectangle shaped empty region with FEOL dummies inserted by blockage-aided FEOL dummy insertion and a related method. This is achieved by the FEOL floorplan and the method according to independent claims, The dependent claims pertain to corresponding further developments and improvements. The invention is set out in the appended set of claims. As will be seen more clearly from the detailed description following below, the claimed FEOL floorplan includes a plurality of FEOL components, a non-rectangle-shaped empty region, a first FEOL dummy, and a second FEOL dummy. The non-rectangle-shaped empty region is located between the plurality of FEOL components, and includes a first empty region in a first direction and a second empty region in a second direction perpendicular to the first direction, wherein the first empty region has a first end connected to the second empty region. The first FEOL dummy is inserted in the first empty region. The second FEOL dummy is inserted in the second empty region. The first FEOL dummy is separated from the second FEOL dummy at the first end of the first empty region. The claimed method of designing an FEOL floorplan of an integrated circuit includes: defining a plurality of FEOL components in the FEOL floorplan, wherein a non-rectangle-shaped empty region is located between the plurality of FEOL components, and includes a first empty region in a first direction and a second empty region in a second direction perpendicular to the first direction, wherein the first empty region has a first end connected to the second empty region; placing a first FEOL blockage at the first end of the first empty region; and running a dummy insertion utility to automatically insert a first FEOL dummy and a second FEOL dummy, wherein the first FEOL blockage assists the dummy insertion utility in inserting the first FEOL dummy in the first empty region only. Brief Description of the Drawings In the following, the invention is further illustrated by way of example, taking reference to the accompanying drawings. Thereof FIG. 1 is a flowchart illustrating a m