EP-4742225-A1 - GOA DRIVING CIRCUIT, DISPLAY PANEL AND DISPLAY APPARATUS

EP4742225A1EP 4742225 A1EP4742225 A1EP 4742225A1EP-4742225-A1

Abstract

A GOA driving circuit (100), a display panel (1) and a display device. The GOA driving circuit (100) includes multiple cascaded GOA units (110), each GOA unit (110) includes a trigger circuit (10), an inverter circuit (20), a pull-up circuit (30) and a pull-down circuit (40). The inverter circuit (20) includes a first thin film transistor (T1) and a second thin film transistor (T2). When a first clock signal (CKL) is at a high level, the trigger circuit (10) and the first thin film transistor (T1) are switched on. When an output of the trigger circuit (10) is at a high level, voltages at two ends of the second thin film transistor (T2) are both at a high level and a through current of the second thin film transistor (T2) is small. When the first clock signal (CKL) is at a low level, the first thin film transistor (T1) is switched off, then the second thin film transistor (T2) is also unable to form the through current.

Inventors

CHEN, CHEN
YUAN, XIN
ZHOU, Xiufeng
XIE, Junfeng

Assignees

HKC CORPORATION LIMITED

Dates

Publication Date: 20260513
Application Date: 20240521

Claims (15)

A GOA driving circuit, comprising multiple cascaded GOA units, each GOA unit comprising: a trigger circuit, wherein an input end of the trigger circuit is configured to receive a start signal or an output signal of a GOA unit at a previous stage, a control end of the trigger circuit is configured to receive a first clock signal, the trigger circuit is triggered to switch on and output the start signal or the output signal when the first clock signal is at a high level, and is triggered to switch off when the first clock signal is at a low level; a pull-up circuit, wherein an input end of the pull-up circuit is configured to receive a second clock signal, an output end of the pull-up circuit serves as a signal output end of the GOA unit, a control end of the pull-up circuit is in connection with an output end of the trigger circuit, the pull-up circuit is triggered by the start signal or the output signal to switch on and output the second clock signal; an inverter circuit, comprising a first thin film transistor and a second thin film transistor, wherein a first end of the first thin film transistor is connected to a positive power supply terminal, a control end of the first thin film transistor and a second end of the second thin film transistor are configured to receive the first clock signal, a second end of the first thin film transistor and a first end of the second thin film transistor are connected in common to constitute an output end of the inverter circuit, a control end of the second thin film transistor is in connection with the output end of the trigger circuit, the first thin film transistor and the second thin film transistor are triggered by a high-level signal to switch on and triggered by a low-level signal to switch off; and a pull-down circuit, wherein an input end of the pull-down circuit is configured to receive a first line switch-off signal, an output end of the pull-down circuit is in connection with the output end of the pull-up circuit, a control end of the pull-down circuit is in connection with the output end of the inverter circuit, and the pull-down circuit is triggered by a high-level signal to switch on.
The GOA driving circuit as claimed in claim 1, wherein the GOA units at multiple stages are respectively connected to corresponding scan lines of an array substrate, the scan lines at multiple stages are connected to multiple rows of pixel units on the array substrate respectively, and the GOA units at multiple stages output line switch-on signals and line switch-off signals to the multiple rows of pixel units row by row.
The GOA driving circuit as claimed in claim 1, wherein the first thin film transistor and the second thin film transistor are N-channel thin film transistors.
The GOA driving circuit as claimed in claim 1, wherein the trigger circuit comprises a third thin film transistor and a fourth thin film transistor; and a first end of the third thin film transistor serves as the input end of the trigger circuit, a second end of the third thin film transistor is in connection with a first end of the fourth thin film transistor, a second end of the fourth thin film transistor serves as the output end of the trigger circuit, and a control end of the third thin film transistor and a control end of the fourth thin film transistor are connected in common to constitute the control end of the trigger circuit.
The GOA driving circuit as claimed in claim 4, wherein the GOA driving circuit further comprises: a reset circuit which is in connection with the output end of the trigger circuit and is triggered by a reset control signal to reset each circuit of the GOA unit; the reset circuit comprises a fifth thin film transistor and a sixth thin film transistor; and a first end of the fifth thin film transistor is configured to receive a second line switch-off signal, a second end of the fifth thin film transistor and a first end of the sixth thin film transistor are connected in common, a second end of the sixth thin film transistor serves as an output end of the reset circuit, and a control end of the fifth thin film transistor and a control end of the sixth thin film transistor are connected in common to receive the reset control signal.
The GOA driving circuit as claimed in claim 5, wherein the first line switch-off signal and the second line switch-off signal are low-level signals.
The GOA driving circuit as claimed in claim 5, wherein the GOA driving circuit further comprises: a stage transfer circuit, wherein an input end of the stage transfer circuit is configured to receive a third clock signal that is inverted from the first clock signal, an output end of the stage transfer circuit is in connection with the input end of the trigger circuit of a GOA unit at a next stage, a control end of the stage transfer circuit is in connection with the output end of the trigger circuit, and the stage transfer circuit is triggered by the high-level signal output from the trigger circuit to switch on and output the third clock signal; and a bootstrap capacitor, wherein the bootstrap capacitor is connected in parallel between the output end and the control end of the stage transfer circuit.
The GOA driving circuit as claimed in claim 7, wherein the stage transfer circuit comprises a seventh thin film transistor, an eighth thin film transistor and a ninth thin film transistor; and a first end of the seventh thin film transistor and a first end of the ninth thin film transistor are connected in common to constitute the input end of the stage transfer circuit, a second end of the seventh thin film transistor, a first end of the eighth thin film transistor, a control end of the ninth thin film transistor and a first end of the bootstrap capacitor are connected in common to constitute the output end of the stage transfer circuit, a control end of the seventh thin film transistor, a second end of the bootstrap capacitor and the output end of the trigger circuit are connected in common, a control end of the eighth thin film transistor is in connection with the output end of the inverter circuit, a second end of the eighth thin film transistor is configured to receive the first line switch-off signal, a second end of the ninth thin film transistor, the second end of the third thin film transistor and the first end of the fourth thin film transistor are connected in common.
The GOA driving circuit as claimed in claim 8, wherein the pull-up circuit comprises a tenth thin film transistor, a first end, a second end and a control end of the tenth thin film transistor respectively serve as the input end, the output end and the control end of the pull-up circuit; and the pull-down circuit comprises an eleventh thin film transistor, a first end, a second end and a control end of the eleventh thin film transistor respectively serve as the input end, the output end and the control end of the pull-down circuit.
The GOA driving circuit as claimed in claim 9, wherein the pull-down circuit further comprises a twelfth thin film transistor, a thirteenth thin film transistor and a coupling capacitor; and a first end of the coupling capacitor is configured to receive the third clock signal, a second end of the coupling capacitor, a control end of the twelfth thin film transistor and a first end of the thirteenth thin film transistor are connected in common, a first end and a second end of the twelfth thin film transistor are respectively connected in parallel to the first end and the second end of the eleventh thin film transistor, a control end of the thirteenth thin film transistor is in connection with the output end of the stage transfer circuit, and a second end of the thirteenth thin film transistor is configured to receive the second line switch-off signal.
The GOA driving circuit as claimed in claim 10, wherein the stage transfer circuit further comprises a fourteenth thin film transistor and a fifteenth thin film transistor; and a control end of the fourteenth thin film transistor is in connection with a second end of the coupling capacitor, a first end and a second end of the fourteenth thin film transistor are respectively connected in parallel to the first end and the second end of the eighth thin film transistor, a first end of the fifteenth thin film transistor is in connection with the output end of the inverter circuit, a second end of the fifteenth thin film transistor is configured to receive the second line switch-off signal, and a control end of the fifteenth thin film transistor is configured to receive the third clock signal.
The GOA driving circuit as claimed in claim 11, wherein during a period when the stage transfer circuit and the pull-down circuit continuously output low-level signals, the eighth thin film transistor and the fourteenth thin film transistor are alternately switched on and off, and the eleventh thin film transistor and the twelfth thin film transistor are alternately switched on and off.
A display panel, comprising an array substrate and the GOA driving circuit as claimed in claim 1, wherein the GOA driving circuit is arranged on one side or both sides of the array substrate.
A display device, comprising a backlight module, a drive circuit board and the display panel as claimed in claim 13, wherein the backlight module and the display panel are arranged opposite to each other, and the drive circuit board is electrically connected to the display panel.
The display device as claimed in claim 14, wherein the backlight module is configured to provide backlight, the drive circuit board is connected to the display panel through a chip-on-chip film, and an external control signal is input to a driving chip in the chip-on-chip film, and the external control signal is converted by the driving chip into a data signal and a control signal required for driving the GOA driving circuit.

Description

This application claims the priority of the Chinese Patent Application No. 202310863346.3, entitled "GOA Driving Circuit, Display Panel and Display Device" filed with the Chinese Patent Office on July 14, 2023, and the entire content of which is incorporated herein by reference. TECHNICAL FIELD The present application relates to the field of display panel technology, more particularly to a GOA driving circuit, a display panel and a display device. BACKGROUND GOA (Gate Driver on Array, gate driver on array substrate) technology integrates the GOA driving circuit" TFT (Thin Film Transistor, thin film field-effect transistor) on an array substrate, thereby the gate driving integrated circuit part originally arranged outside the array substrate is eliminated, and thus the cost of the product is reduced from both the material cost and process steps aspects. The GOA driving circuit usually includes multiple cascaded GOA units. The commonly-used GOA unit is shown in FIG. 1, which usually includes an inverter module, a reset module, a trigger module and an output module. The inverter module is used to achieve an inversion conversion from a pull-up control signal PU to a pull-down control signal PD. However, in the inverter module, T6 is switched on to pull PD node down when PU is set high, at this time, T5 is in an on state, which will cause a through-conduction current between Vgh and Vgl, resulting in an abnormal GOA unit, and then causing an abnormal display on the display panel. SUMMARY TECHNICAL PROBLEM An objective of the present application is to provide a GOA driving circuit, which aims to address the problem of display panel display abnormalities caused by the through-conduction current in the inverter module of traditional GOA units. TECHNICAL SOLUTIONS To solve the above technical problem, technical solutions adopted by the embodiments of the present application are as follows: In accordance with a first aspect of the embodiments of the present application, a GOA driving circuit is provided, which includes multiple cascaded GOA units, and each GOA unit includes: a trigger circuit, an input end of the trigger circuit is configured to receive a start signal or an output signal of a GOA unit at a previous stage, a control end of the trigger circuit is configured to receive a first clock signal, the trigger circuit is triggered to switch on and output the start signal or the output signal when the first clock signal is at a high level, and is triggered to switch off when the first clock signal is at a low level;a pull-up circuit, an input end of the pull-up circuit is configured to receive a second clock signal, an output end of the pull-up circuit serves as a signal output end of the GOA unit, a control end of the pull-up circuit is in connection with an output end of the trigger circuit, the pull-up circuit is triggered by the start signal or the output signal to switch on and output the second clock signal;an inverter circuit which includes a first thin film transistor and a second thin film transistor, a first end of the first thin film transistor is connected to a positive power supply terminal, a control end of the first thin film transistor and a second end of the second thin film transistor are configured to receive the first clock signal, a second end of the first thin film transistor and a first end of the second thin film transistor are connected in common to constitute an output end of the inverter circuit, a control end of the second thin film transistor is in connection with an output end of the trigger circuit, the first thin film transistor and the second thin film transistor are triggered by a high-level signal to switch on and triggered by a low-level signal to switch off; anda pull-down circuit, an input end of the pull-down circuit is configured to receive a first line switch-off signal, an output end of the pull-down circuit is in connection with the output end of the pull-up circuit, a control end of the pull-down circuit is in connection with the output end of the inverter circuit, and the pull-down circuit is triggered by a high-level signal to switch on. Optionally, the GOA units at multiple stages are respectively connected to corresponding scan lines of an array substrate, and the scan lines at multiple stages are connected to the multiple rows of pixel units on the array substrate, and the GOA units at multiple stages output row-on signals and row-off signals to the multiple rows of pixel units row by row. Optionally, the first thin film transistor and the second thin film transistor are N-channel thin film transistors. Optionally, the trigger circuit includes a third thin film transistor and a fourth thin film transistor. A first end of the third thin film transistor serves as the input end of the trigger circuit, a second end of the third thin film transistor is in connection with a first end of the fourth thin film transistor, a second end of the fourth thin film transistor ser