EP-4742226-A1 - DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE

EP4742226A1EP 4742226 A1EP4742226 A1EP 4742226A1EP-4742226-A1

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a plurality of circuit units; each circuit unit comprises a pixel driving circuit, a first scanning signal line (31), a second scanning signal line (32), a third scanning signal line (33), and a light-emitting signal line (35); the pixel driving circuit comprises at least an eighth transistor (T8) and a ninth transistor (T9); the orthographic projection of the first scanning signal line (31) on the plane of the display substrate is at least partially overlapped with the orthographic projection of the second scanning signal line (32) on the plane of the display substrate; the orthographic projection of the third scanning signal line (33) on the plane of the display substrate is at least partially overlapped with the orthographic projection of the light-emitting signal line (35) on the plane of the display substrate; and the orthographic projection of the eighth transistor (T8) on the plane of the display substrate is at least partially overlapped with the orthographic projection of the ninth transistor (T9) on the plane of the display substrate.

Inventors

ZHAO, Jiao
GUAN, FENG
DU, JIANHUA
LV, Yang
WANG, Chaolu
WANG, YICHENG
YAN, Rui
WU, HAO
XIAO, LI
ZHAO, MENG
GUO, Yuzhen
ZHANG, CHENYANG
CUI, Xiaorong
GAO, Lipeng
ZHENG, HAOLIANG
XUAN, MINGHUA
ZHOU, YING

Assignees

Boe Technology Group Co., Ltd.
Beijing BOE Technology Development Co., Ltd.

Dates

Publication Date: 20260513
Application Date: 20230831

Claims (20)

A display substrate, comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, wherein at least one circuit unit comprises a pixel drive circuit, a first scan signal line, a second scan signal line, a third scan signal line, and a light emitting signal line, the pixel drive circuit at least comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; a gate electrode of the first transistor, a gate electrode of the seventh transistor and a gate electrode of the tenth transistor are electrically connected to the third scan signal line, a gate electrode of the second transistor is electrically connected to the second scan signal line, a gate electrode of the fourth transistor is electrically connected to the first scan signal line, a gate electrode of the fifth transistor is electrically connected to the light emitting signal line, and a gate electrode of the eighth transistor is electrically connected to a gate electrode of the ninth transistor; an orthographic projection of the first scan signal line on a plane of the display substrate at least partially overlaps an orthographic projection of the second scan signal line on the plane of the display substrate, an orthographic projection of the third scan signal line on the plane of the display substrate at least partially overlaps an orthographic projection of the light emitting signal line on the plane of the display substrate, and an orthographic projection of the eighth transistor on the plane of the display substrate at least partially overlaps an orthographic projection of the ninth transistor on the plane of the display substrate.
The display substrate according to claim 1, wherein the first transistor, the second transistor, the seventh transistor, the ninth transistor, and the tenth transistor are oxide transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the eighth transistor are polysilicon transistors.
The display substrate according to claim 1, wherein an orthographic projection of the gate electrode of the eighth transistor on the plane of the display substrate at least partially overlaps an orthographic projection of the gate electrode of the ninth transistor on the plane of the display substrate.
The display substrate according to claim 1, wherein an orthographic projection of an active layer of the eighth transistor on the plane of the display substrate at least partially overlaps an orthographic projection of an active layer of the ninth transistor on the plane of the display substrate.
The display substrate according to claim 1, wherein an orthographic projection of a channel region of the eighth transistor on the plane of the display substrate at least partially overlaps an orthographic projection of a channel region of the ninth transistor on the plane of the display substrate.
The display substrate according to claim 1, wherein, in at least one unit row, pixel drive circuits in two adjacent circuit units are mirror symmetrical with respect to a column dividing line, which is a straight line located between adjacent unit columns and extending in a pixel column direction.
The display substrate according to claim 1, wherein, in at least one unit column, pixel drive circuits in two adjacent circuit units are mirror symmetrical with respect to a row dividing line which is a straight line located between adjacent unit rows and extending in a pixel row direction.
The display substrate according to claim 1, wherein, in at least one unit column, first electrodes of first transistors in two adjacent circuit units are connected to a same initial signal line, and first electrodes of seventh transistors in two adjacent circuit units are connected to a same initial signal line.
The display substrate according to claim 1, wherein, in at least one unit column, active layers of first transistors in two adjacent circuit units are of an interconnected integral structure, and active layers of seventh transistors in two adjacent circuit units are of an interconnected integral structure.
The display substrate according to claim 1, wherein, in at least one unit row, first electrodes of eighth transistors in two adjacent circuit units are connected to a same high-frequency signal line.
The display substrate according to claim 1, wherein, in at least one unit row, active layers of eighth transistors in two adjacent circuit units are of an interconnected integral structure.
The display substrate according to any one of claims 1 to 11, wherein, in a direction perpendicular to the display substrate, the display substrate comprises a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer that are sequentially disposed on a base substrate; an active layer of the third transistor, an active layer of the fourth transistor, an active layer of the fifth transistor, an active layer of the sixth transistor and an active layer of the eighth transistor are disposed in the first semiconductor layer, the first scan signal line, the light emitting signal line and the gate electrode of the eighth transistor are disposed in the first conductive layer, an active layer of the first transistor, an active layer of the second transistor, an active layer of the seventh transistor, an active layer of the ninth transistor and an active layer of the tenth transistor are disposed in the second semiconductor layer, and the second scan signal line, the third scan signal line and the gate electrode of the ninth transistor are disposed in the third conductive layer.
The display substrate according to claim 12, wherein the display substrate further comprises a first shielding line disposed between the third scan signal line and the light emitting signal line in the direction perpendicular to the display substrate, an orthographic projection of the first shielding line on the base substrate at least partially overlaps an orthographic projection of the light emitting signal line on the base substrate, and the orthographic projection of the first shielding line on the base substrate at least partially overlaps an orthographic projection of the third scan signal line on the base substrate.
The display substrate according to claim 12, wherein the display substrate further comprises a second shielding line disposed between the first scan signal line and the second scan signal line in the direction perpendicular to the display substrate, an orthographic projection of the second shielding line on the base substrate overlaps at least partially an orthographic projection of the first scan signal line on the base substrate, and the orthographic projection of the second shielding line on the base substrate overlaps at least partially an orthographic projection of the second scan signal line on the base substrate.
The display substrate according to claim 12, wherein the display substrate further comprises a fourth conductive layer disposed on a side of the third conductive layer away from the base substrate; the fourth conductive layer at least comprises an interconnection electrode connected with the active layer of the eighth transistor and the active layer of the ninth transistor, respectively.
The display substrate according to claim 15, wherein one end of the interconnection electrode is connected to the active layer of the eighth transistor through one via, and the other end of the interconnection electrode is connected to the active layer of the ninth transistor through another via.
The display substrate according to claim 15, wherein the interconnection electrode is lapped with a first surface of the active layer of the eighth transistor through one lap hole and lapped with a second surface of the active layer of the ninth transistor through the lap hole, the first surface is a surface parallel to the base substrate, and the second surface is a surface intersecting the base substrate.
The display substrate according to claim 15, wherein the third conductive layer further comprises a transfer electrode; the transfer electrode is connected to the active layer of the eighth transistor through one transfer hole, one end of the interconnection electrode is connected to a first transfer electrode through one via, and the other end of the interconnection electrode is connected to the active layer of the ninth transistor through another via.
The display substrate according to claim 15, wherein the display substrate further comprises a shielding layer disposed between the first conductive layer and the second conductive layer, the shielding layer comprises a transfer electrode; the transfer electrode is connected to the active layer of the eighth transistor through one transfer hole, one end of the interconnection electrode is connected to the transfer electrode through one via, and the other end of the interconnection electrode is connected to the active layer of the ninth transistor through another via.
The display substrate according to claim 12, wherein the second conductive layer comprises a transfer electrode; the transfer electrode is connected to the active layer of the eighth transistor through one transfer hole, and the active layer of the ninth transistor is connected to the transfer electrode through another transfer hole.

Description

Technical Field The present disclosure relates to, but is not limited to, the field of display technologies, and particularly to a display substrate and a preparation method therefor, and a display apparatus. Background A Light Emitting Diode (LED) technology has been developed for nearly 30 years, from an initial solid lighting power supply to a backlight in the display field, and then to an LED display screen, providing a solid foundation for its wider applications. With development of chip manufacturing and encapsulation technologies, Mini Light Emitting Diode (Mini LED) display and Micro Light Emitting Diode (Micro LED) display have gradually become a hot spot in a display panel, and may be applied in fields such as Augmented Reality / Virtual Reality (AR/VR), Television (TV), and outdoor display. Summary The following is a summary of subject matter described herein in detail. The summary is not intended to limit the scope of protection of the claims. In one aspect, an embodiment of the present disclosure provides a display substrate including a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns. At least one circuit unit includes a pixel drive circuit, a first scan signal line, a second scan signal line, a third scan signal line, and a light emitting signal line, the pixel drive circuit at least includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor. A gate electrode of the first transistor, a gate electrode of the seventh transistor and a gate electrode of the tenth transistor are electrically connected to the third scan signal line, a gate electrode of the second transistor is electrically connected to the second scan signal line, a gate electrode of the fourth transistor is electrically connected to the first scan signal line, a gate electrode of the fifth transistor is electrically connected to the light emitting signal line, and a gate electrode of the eighth transistor is electrically connected to a gate electrode of the ninth transistor; an orthographic projection of the first scan signal line on a plane of the display substrate at least partially overlaps an orthographic projection of the second scan signal line on the plane of the display substrate, an orthographic projection of the third scan signal line on the plane of the display substrate at least partially overlaps an orthographic projection of the light emitting signal line on the plane of the display substrate, and an orthographic projection of the eighth transistor on the plane of the display substrate at least partially overlaps an orthographic projection of the ninth transistor on the plane of the display substrate. In an exemplary implementation, the first transistor, the second transistor, the seventh transistor, the ninth transistor, and the tenth transistor are oxide transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the eighth transistor are polysilicon transistors. In an exemplary implementation, an orthographic projection of the gate electrode of the eighth transistor on the plane of the display substrate overlaps at least partially an orthographic projection of the gate electrode of the ninth transistor on the plane of the display substrate. In an exemplary implementation, an orthographic projection of an active layer of the eighth transistor on the plane of the display substrate at least partially overlaps an orthographic projection of an active layer of the ninth transistor on the plane of the display substrate. In an exemplary implementation, an orthographic projection of a channel region of the eighth transistor on the plane of the display substrate at least partially overlaps an orthographic projection of a channel region of the ninth transistor on the plane of the display substrate. In an exemplary implementation, in at least one unit row, pixel drive circuits in two adjacent circuit units are mirror symmetrical with respect to a column dividing line, which is a straight line located between adjacent unit columns and extending in a pixel column direction. In an exemplary implementation, in at least one unit column, pixel drive circuits in two adjacent circuit units are mirror symmetrical with respect to a row dividing line which is a straight line located between adjacent unit rows and extending in a pixel row direction. In an exemplary implementation, in at least one unit column, first electrodes of first transistors in two adjacent circuit units are connected to a same initial signal line, and first electrodes of seventh transistors in two adjacent circuit units are connected to a same initial signal line. In an exemplary implementation, in at least one unit column, active layers of first transistors in two adjacent circuit units are of an interconnected integ