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EP-4742230-A1 - TRANSISTOR AND DISPLAY DEVICE INCLUDING THE SAME

EP4742230A1EP 4742230 A1EP4742230 A1EP 4742230A1EP-4742230-A1

Abstract

A display device includes a substrate (111) including a first area (AAl) including first subpixels (SP1) and a transmissive part (TA), and a second area (AA") including second subpixels (SP2). A first transistor (T1) in the first area (A1) includes an oxide semiconductor active layer (ACT1), a gate electrode (G1), and first and second source-drain electrodes (SD11, SD12). A second transistor (T2) disposed in the first area (AA1) includes an oxide semiconductor active layer (ACT2) including first and second active layers (A21, A22), a gate electrode (G2), and first and second source-drain electrodes (SD21, SD22). A light-emitting element (135) is disposed in the first area (AA1). A third transistor (T3) is connected between the second transistor (T2) and the light-emitting element (135) and includes an oxide semiconductor active layer (ACT3) including first and second active layers (A31, A32), a gate electrode (G3), and first and second source-drain electrodes (SD31, SD32). The second active layer (A32) of the third transistor (T3) has a higher carrier mobility than the first active layer (A31) of the third transistor (T3).

Inventors

  • IM, SEO YEON

Assignees

  • LG Display Co., Ltd.

Dates

Publication Date
20260513
Application Date
20250930

Claims (15)

  1. A transistor (T2, T3, T4) comprising: an active layer (ACT) comprising an oxide semiconductor material, the active layer (ACT) including a first active layer (A1) and a second active layer (A2) contacting the first active layer (A1), the second active layer (A2) having a higher carrier mobility than a carrier mobility of the first active layer (A1); a gate electrode (G) overlapping at least a portion of the first active layer (A1) and at least a portion of the second active layer (A2) of the active layer (ACT) to form a channel region (CA); a first source-drain electrode (SD1) insulated from the gate electrode (G) and connected to another portion of the second active layer (A2) not overlapping the gate electrode (G); and a second source-drain electrode (SD2) insulated from the gate electrode (G) and connected to another portion of the first active layer (A1) not overlapping the gate electrode (G).
  2. The transistor (T2, T3, T4) according to claim 1, wherein the first active layer (A1) and the second active layer (A2) directly contact an upper surface of a common insulating layer in an area overlapping the gate electrode (G).
  3. The transistor (T2, T3, T4) according to claim 1 or 2, wherein the channel region (CA) comprises: a first channel region (CA1) where the gate electrode (G) and the first active layer (A1) overlap each other; and a second channel region (CA2) where the gate electrode (G) and the second active layer (A2) overlap each other.
  4. The transistor (T2, T3, T4) according to claim 3, wherein a length of the second channel region (CA2) is greater than a length of the first channel region (CA1).
  5. The transistor (T2, T3, T4) according to claim 3 or 4, wherein at least a portion of the first channel region (CA1) does not overlap with at least a portion of the second active layer (A2).
  6. The transistor (T2, T3, T4) according to any of claims 1 to 5, wherein a length of the second active layer (A2) overlapped by the gate electrode (G) is greater than a length of the first active layer (A1) overlapped by the gate electrode (G).
  7. The transistor (T2, T3, T4) according to any of claims 1 to 6, wherein at least a portion of the first active layer (A1) extends up to a portion of an upper surface of the second active layer (A2) to cover at least the portion of the upper surface of the second active layer (A2), or wherein at least a portion of the second active layer (A2) extends up to a portion of an upper surface of the first active layer (A1) to cover at least the portion of the upper surface of the first active layer (A1).
  8. The transistor (T2, T3, T4) according to any of claims 1 to 6, wherein: the second active layer (A2) comprises a second lower active layer (A2a) disposed beneath the first active layer (A1), and a second upper active layer (A2b) disposed on an upper surface of the first active layer (A1), and a length of the second upper active layer (A2b) of the second active layer (A2) is less than a length of the second lower active layer (A2a) of the second active layer (A2); or wherein: the first active layer (A1) comprises a first lower active layer (A1a) disposed beneath the second active layer (A2), and a first upper active layer (Alb) disposed on an upper surface of the second active layer (A2), and a length of the first upper active layer (A1b) of the first active layer (A1) is less than a length of the first lower active layer (A1a) of the first active layer (A1).
  9. The transistor (T2, T3, T4) according to any of claims 1 to 8, further comprising: a lower metal (LS) disposed beneath the active layer (ACT) and electrically connected to the first source-drain electrode (SD1).
  10. The transistor (T2, T3, T4) according to any of claims 1 to 9, wherein the active layer (ACT) comprises a structure with the first active layer (A1) and the second active layer (A2) alternately stacked at a central portion of the channel region (CA).
  11. A display device comprising: a substrate (111) comprising a first area (AA1) comprising a plurality of first subpixels (SP1) and a transmissive part (TA), and a second area (AA2) comprising a plurality of second subpixels (SP2) without a transmissive part; a light-emitting element (135) at the first area (AA1); and a transistor (T3) according to any of claims 1 to 10, connected to the light-emitting element (135) at the first area (AA1) with the transmissive part (TA).
  12. The display device of claim 11, wherein the transistor (T3) is a third transistor (T3), the display device further comprising: a first transistor (T1) disposed in the first area (AA1) with the transmissive part (TA), the first transistor (T1) comprising an active layer (ACT1) comprising an oxide semiconductor material, a gate electrode (G1), and a first source-drain electrode (SD11) and a second source-drain electrode (SD12); and a second transistor (T2) disposed in the first area (AA1) with the transmissive part (TA), the second transistor (T2) comprising an active layer (ACT2) comprising a first active layer (A21) and a second active layer (A22) each comprising an oxide semiconductor material, a gate electrode (G2), a first source-drain electrode (SD21), and a second source-drain electrode (SD22); wherein the third transistor (T3) is electrically connected between the second transistor (T2) and the light-emitting element (135), wherein, optionally: the first transistor (T1) is a switching transistor, the second transistor (T2) is a driving transistor, and the third transistor (T3) is a light-emitting transistor.
  13. The display device according to claim 12, wherein the second source-drain electrode (SD32) of the third transistor (T3) is connected to the first active layer (A31) of the third transistor (T3), and the second source-drain electrode (SD2) of the third transistor (T3) is electrically connected to a first electrode (E1) of the light-emitting element (135).
  14. The display device according to claim 13, wherein a flow direction of current during operation of the third transistor (T3) proceeds toward the first electrode (E1) in an order of the first source-drain electrode (SD31) of the third transistor (T3), the second active layer (A32) of the third transistor (T3), the first active layer (A31) of the third transistor (T3) having a lower mobility than the mobility of the second active layer (A32) of the third transistor (T3), and the second source-drain electrode (SD32) of the third transistor (T3).
  15. The display device according to any of claims 12 to 14, wherein the active layer (ACT1) of the first transistor (T1) has a carrier mobility lower than or equal to the carrier mobility of the first active layer (A31) of the third transistor (T3); and/or wherein: a carrier mobility of the second active layer (A22) of the second transistor (T2) is higher than a carrier mobility of the first active layer (A21) of the second transistor (T2), the first source-drain electrode (SD21) of the second transistor (T2) is connected to the second active layer (A22) of the second transistor (T2), and the second source-drain electrode (SD22) of the second transistor (T2) is connected to the first active layer (A21) of the second transistor (T2).

Description

BACKGROUND Field of the Disclosure The present disclosure relates to a transistor and a display device including the same. Discussion of the Related Art Display devices configured to display images in TVs, monitors, smartphones, tablets, laptops, etc. use various systems and forms. Among display devices, a light-emitting display device having light-emitting elements in a display panel without a separate light source is considered as a competitive application for compactness and sharp color representation. Display devices commonly employ transistors to perform various different functions. For example, a display device can include an active area having a plurality of pixels to implement images are equipped with transistors configured to control pixel operation on a pixel basis. In contrast, in a non-active area surrounding the plurality of pixels, the display device can include transistors serving other functions, such as providing data and control signals to the plurality of pixels. However, transistors used for different functions can require different characteristics and, as such, structural differences of between various transistors are necessary. On the other hand, it is advantageous to form all of the various transistors by the same processes to reduce processing steps. Accordingly, display devices having transistors with structural differences but made by the same process are desirable. SUMMARY OF THE DISCLOSURE Accordingly, the present disclosure is directed to a transistor and a display device including the same substantially obviate one or more problems due to limitations and disadvantages of the related art. An object according to various embodiments of the present disclosure is to provide a transistor capable of reducing occurrence of a hot carrier stress phenomenon, and a display device including the transistor. Another object according to various embodiments of the present disclosure is to provide a transistor capable of increasing the area of a transmissive part of a display area and enhancing transmittance, and a display device including the transistor. Still another object according to various embodiments of the present disclosure is to provide a transistor capable of enhancing picture quality while providing high luminance, and a display device including the transistor. Yet another object according to various embodiments of the present disclosure is to differently set an S-factor and an on-current value in accordance with the function of a transistor. Still further, yet another object is to provide a transistor which is advantageous, stable, and finely controllable for gradation representation, and a display device including the transistor. Furthermore, an additional object is to achieve environmental/social/governance (ESG) goals by enhancing reliability of a transistor and reducing power consumption of the transistor. Objects of the present disclosure are not limited to the above-described objects, and other objects of the present disclosure not yet described will be more clearly understood by those skilled in the art from the following description. To achieve these objects and other advantages and in accordance with the purpose of the disclosure, as embodied and broadly described herein, there is provided a transistor according to claim 1. Further embodiments are described in the dependent claims. A transistor according to an embodiment of the present disclosure can include an active layer including a first active layer including an oxide semiconductor material and a second active layer having a higher carrier mobility than a carrier mobility of the first active layer, a gate electrode disposed to overlap with the active layer to form a channel region of the active layer, a first source-drain electrode insulated from the gate electrode and connected to the second active layer, and a second source-drain electrode insulated from the gate electrode and connected to the first active layer. A transistor according to another embodiment of the present disclosure can comprise an active layer including a region where the second active layer and the gate electrode do not overlap each other. The first active layer and the second source-drain electrode can be connected to each other in the region where the second active layer and the gate electrode do not overlap each other. The second active layer and the first source-drain electrode can be connected to each other in a region where the first active layer and the gate electrode do not overlap each other. The channel region can include a first channel region where the gate electrode and the first active layer overlap each other, and a second channel region where the gate electrode and the second active layer overlap each other. The length of the second channel region can be greater than the length of the first channel region. In other embodiments, a transistor can comprise at least a portion of the first channel region not overlapping with at least a