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EP-4742231-A2 - DISPLAY PANEL AND DISPLAY DEVICE

EP4742231A2EP 4742231 A2EP4742231 A2EP 4742231A2EP-4742231-A2

Abstract

Provided is a display panel (10), including: a base substrate (101); a first auxiliary electrode layer (102), a first anode layer (103), a first light-emitting layer (104) and a first cathode layer (105) that are stacked in sequence, in a direction away from the base substrate (101), in the first display region (101a); and a second auxiliary electrode layer (106), a second anode layer (107), a second light-emitting layer (108), and a second cathode layer (109) that are sequentially laminated, in the direction away from the base substrate (101), in the second display region (101b); wherein the first auxiliary electrode layer (102) is connected to the first cathode layer (105) and the second auxiliary electrode layer (106), and the second cathode layer (109) is connected to the first cathode layer (105), the second cathode layer (109) is provided with at least one through hole.

Inventors

  • LIU, CHANGCHANG
  • SHI, LING
  • LIU, KE
  • CHEN, Yipeng
  • ZHANG, ZHENHUA
  • LU, HUI

Assignees

  • BOE Technology Group Co., Ltd.
  • Chengdu BOE Optoelectronics Technology Co., Ltd.

Dates

Publication Date
20260513
Application Date
20210224

Claims (15)

  1. A display panel (10), comprising: a base substrate (101) with a first display region (101a) and a second display region (101b), wherein the first display region (101a) is adjacent to the second display region (101b), and a transmittance of the display panel (10) corresponding to the second display region (101b) is greater than a transmittance of the display panel (10) corresponding to the first display region (101a); a first auxiliary electrode layer (102), a first anode layer (103), a first light-emitting layer (104) and a first cathode layer (105) that are stacked in sequence, in a direction away from the base substrate (101), in the first display region (101a); and a second auxiliary electrode layer (106), a second anode layer (107), a second light-emitting layer (108), and a second cathode layer (109) that are stacked in sequence, in the direction away from the base substrate (101), in the second display region (101b); wherein the first auxiliary electrode layer (102) is electrically connected to the first cathode layer (105) and the second auxiliary electrode layer (106), the second cathode layer (109) is electrically connected to the first cathode layer (105), and the second cathode layer (109) has at least one through hole; wherein the display panel (10) further comprises pixel circuits (110) in the second display region (101b), and each of the pixel circuits (110) comprising at least one layer of opaque patterns (b); wherein the second auxiliary electrode layer (106) comprises auxiliary electrode patterns (1061) electrically connected; and an orthographic projection of the at least one layer of opaque patterns (b) in at least one of the pixel circuits (110) is at least partially within orthographic projections of the auxiliary electrode patterns (1061) onto base substrate (101).
  2. The display panel (10) according to claim 1, wherein the orthographic projections of the auxiliary electrode patterns (1061) onto the base substrate (101) completely cover the orthographic projections of the at least one layer of opaque patterns (b) in at least one of the pixel circuits (110) onto the base substrate (101).
  3. The display panel (10) according to claim 2, wherein the at least one layer of opaque patterns (b) comprises layers of opaque patterns (b); the layers of opaque patterns (b) comprise an overlap (c1) and a non-overlap (c2), wherein an orthographic projection of the overlap (c1) onto the base substrate (101) is at least partially within the orthographic projections of the auxiliary electrode patterns (1061) onto the base substrate (101), and an orthographic projection of the non-overlap (c2) onto the base substrate (101) is at least partially within the orthographic projections of the auxiliary electrode patterns (1061) onto the base substrate (101); optionally, the orthographic projection of the overlap (c1) onto the base substrate (101) is entirely within the orthographic projections of the auxiliary electrode patterns (1061) onto the base substrate (101).
  4. The display panel (10) according to any one of claims 1 to 3, wherein an edge of an orthographic projection of each auxiliary electrode pattern (1061) of the auxiliary electrode patterns (1061) onto the base substrate (101) is at least partially arc-shaped; optionally, the edge of the orthographic projection of the each auxiliary electrode pattern (1061) onto the base substrate (101) comprises an arc line segment, a ratio of a length of the arc line segment to a perimeter of the edge being greater than or equal to 50%.
  5. The display panel (10) according to any one of claims 1 to 4, wherein each of the auxiliary electrode patterns (1061) comprises a first pattern (10611) and a second pattern (10612); an orthographic projection of the first pattern (10611) onto the base substrate (101) overlaps 50% or more of areas of the orthographic projection of the at least one layer of opaque patterns (b) in at least one of the pixel circuits (110) onto the base substrate (101); and the second pattern (10612) is electrically connected to an auxiliary electrode pattern (1061) adjacent to the second pattern (10612); optionally, the orthographic projection of the first pattern (10611) onto the base substrate (101) is circular.
  6. The display panel (10) according to any one of claims 1 to 5, wherein the base substrate (101) has a peripheral region (101c) surrounding both the first display region (101a) and the second display region (101b); and the first auxiliary electrode layer (102) and the first cathode layer (105) are in the peripheral region (101c), and a portion of the first auxiliary electrode layer (102) in the peripheral region (101c) is electrically connected to a portion of the first cathode layer (105) in the peripheral region (101c); optionally, an orthographic projection of the first auxiliary electrode layer (102) onto the base substrate (101) completely covers the first display region (101a); wherein the peripheral region (101c) comprises a first region (101c1) and a second region (101c2) that are arranged opposite to each other, and a third region (101c3) and a fourth region (101c4) that are arranged opposite to each other, a lengthwise direction in which the first region (101c1) extends is perpendicular to a lengthwise direction in which the third region (101c3) extends, and the second display region (101b) is closer to the first region (101c1) relative to the second region (101c2).
  7. The display panel (10) according to any one of claims 1 to 6, wherein the auxiliary electrode patterns (1061) overlap one another.
  8. The display panel (10) according to any one of claims 1 to 7, further comprising first connection electrodes (124) in the second display region (101b), wherein the auxiliary electrode patterns (1061) are electrically connected by the first connection electrodes (124).
  9. The display panel (10) according to any one of claims 1 to 8, further comprising an active layer (112), a buffer layer (111), a first gate insulation layer (114), a first gate layer (113), a second gate insulation layer (116), a second gate layer (115), an interlayer dielectric layer (117) and a first source/drain layer (118) that are stacked in sequence, in the direction away from the base substrate (101), in both the first display region (101a) and the second display region (101b); the first source/drain layer (118) comprises sets of first source/drain layer patterns corresponding to the pixel circuits (110), the active layer (112) comprises sets of active patterns (1131) corresponding to the pixel circuits (110), the first gate layer (113) comprises sets of first gate patterns (1151) corresponding to the pixel circuits (110), and the second gate layer (115) comprises sets of second gate patterns corresponding to the pixel circuits (110); and the at least one layer of opaque patterns (b) in each of the pixel circuits (110) comprises one set of the first source/drain layer patterns in the first source/drain layer (118), one set of the active patterns (1131) in the active layer (112), one set of the first gate patterns (1151) in the first gate layer (113), and one set of the second gate patterns disposed in the second gate layer (115).
  10. The display panel (10) according claim 9, further comprising a first conduction layer (125) in a same layer as the first source/drain layer (118), and a second conduction layer (126) in a same layer as the second gate layer (115), wherein there is a first via hole extending through the buffer layer (111), the first gate insulation layer (114), the second gate insulation layer (116) and the interlayer dielectric layer (117), the second conduction layer (126) and the first conduction layer (125) being electrically connected to the auxiliary electrode patterns (1061) through the first via holes; and wherein display panel (10) further comprises a passivation layer (119) and a first planarization layer (120) that are on a side, distal from the base substrate (101), of the first source/drain layer (118), and first connection electrodes (124) between the passivation layer (119) and the first planarization layer (120); wherein the passivation layer (119) has a second via hole, at least part of the first connection electrodes (124) is in the second via hole and connected to the first conduction layer (125), and the first connection electrodes (124) are connected to the auxiliary electrode patterns (1061).
  11. The display panel (10) according to claim 9, further comprising a passivation layer (119) and a first planarization layer (120) that are on a side, distal from the base substrate (101), of the first source/drain layer (118), second connection electrodes (127) between the passivation layer (119) and the first planarization layer (120), a first signal transmission layer (128) in a same layer as the first source/drain layer (118), and a third conduction layer (129) in a same layer as the first gate layer (113); wherein there is a third via hole extending through the first gate insulation layer (114), the second gate insulation layer (116) and the interlayer dielectric layer (117), and the first signal transmission layer (128) is electrically connected to the third conduction layer (129) through the third via hole; and wherein the passivation layer (119) has a fourth via hole, and at least part of the second connection electrodes (127) is in the fourth via hole and connected to the first signal transmission layer (128).
  12. The display panel (10) according to claim 9, further comprising third connection electrodes (130), and a fourth conduction layer (131), wherein the fourth conduction layer (131) comprises fourth signal line segments (1311); wherein each of the fourth signal line segments (1311) is connected to at least one of the pixel circuits (110), and at least part of the fourth signal line segments (1311) is electrically connected by at least part of the third connection electrodes (130).
  13. The display panel (10) according to any one of claims 1 to 8, further comprising an active layer (112), a buffer layer (111), a first gate insulation layer (114), a first gate layer (113), a second gate insulation layer (116), a second gate layer (115), an interlayer dielectric layer (117), a first source/drain layer (118), a passivation layer (119) and a first planarization layer (120) that are stacked in sequence, in the direction away from the base substrate (101), in both the first display region (101a) and the second display region (101b); wherein the display panel (10) further comprises connection electrodes between the passivation layer (119) and the first planarization layer (120); at least part of the connection electrodes is electrically connected to at least two of the auxiliary electrode patterns (1061) in the second display region (101b); wherein the connection electrodes comprise joints, the joints comprise connection via holes or lap structures, corresponding to the connection electrodes and patterns connected by the connection electrodes, and the orthographic projections of the auxiliary electrode patterns (1061) onto the base substrate (101) is overlapped with an orthographic projection of at least one of the joints onto the base substrate (101).
  14. The display panel (10) according to any one of claims 1 to 13, wherein the second anode layer (107) comprises anode patterns spaced apart from each other, and the display panel (10) further comprises a pixel definition layer (134) on a side, distal from the base substrate (101), of the second anode layer (107); the pixel definition layer (134) comprises tenth via holes, through which corresponding anode patterns are exposed, and the second light-emitting layer (108) comprises light-emitting layer patterns (1081) at least partially in the tenth via holes; and the second cathode layer (109) at least partially covers the tenth via holes, and the at least one through hole of the second cathode layer (109) is not overlapped with the tenth via holes; optionally, the second cathode layer (109) comprises cathode patterns (1091), the cathode patterns (1091) overlap one another, and at least one through hole is formed by the cathode patterns (1091) that are overlapped with one another; wherein an orthographic projection of each of the cathode patterns (1091) onto the base substrate (101) completely covers an orthographic projection of at least one of the light-emitting layer patterns (1081) onto the base substrate (101).
  15. A display device, comprising an image sensor (40) and the display panel (10) as defined in any one of claims 1 to 14, wherein the image sensor (40) is disposed on a side, distal from the second auxiliary electrode layer (106), of the base substrate (101) in the display panel (10), and is overlapped with the second display region (101b) of the base substrate (101).

Description

TECHNICAL FIELD The present disclosure relates to the field of display technologies and in particular relates to a display panel and a display device. BACKGROUND Organic light-emitting diode (OLED) display panels have been widely used due to their advantages of self-luminescence, low driving voltage, fast response, etc. SUMMARY The present disclosure provides a display panel and a display device. The technical solutions are described as below. In some embodiments of the present disclosure, a display panel is provided. The display panel includes: a base substrate provided with both a first display region and a second display region;a first auxiliary electrode layer, a first anode layer, a first light-emitting layer, and a first cathode layer that are stacked in sequence, in a direction away from the base substrate, in the first display region; anda second auxiliary electrode layer, a second anode layer, a second light-emitting layer and a second cathode layer that are stacked in sequence, in the direction away from the base substrate, in the second display region;wherein the first auxiliary electrode layer is connected to the first cathode layer and the second auxiliary electrode layer, and the second cathode layer is connected to the first cathode layer, the second cathode layer is provided with at least one through hole;the display panel further includes a plurality of pixel circuits disposed in the second display region, and each of the pixel circuits includes at least one layer of opaque patterns; wherein the second auxiliary electrode layer includes a plurality of auxiliary electrode patterns electrically connected; and at least 50% of regions of orthographic projections of the at least one layer of opaque patterns in at least one of the pixel circuits onto the base substrate is overlapped with orthographic projections of the auxiliary electrode patterns onto the base substrate. In some embodiments of the present disclosure, a display device is provided. The display device includes an image sensor and the display panel as described in the foregoing aspect, wherein the image sensor is disposed on a side, distal from a second anode layer, of a base substrate in the display panel and is overlapped with a second display region of the base substrate. BRIEF DESCRIPTION OF THE DRAWINGS For clearer descriptions of the technical solutions in the embodiments of the present disclosure, the following briefly introduces the accompanying drawings required for describing the embodiments. Apparently, the accompanying drawings in the following description show merely some embodiments of the present disclosure, and a person of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts. FIG. 1 is a schematic structural diagram of a display panel according to some embodiments of the present disclosure;FIG. 2 is a top view of a base substrate according some embodiments of the present disclosure;FIG. 3 is a schematic structural diagram of another display panel according to some embodiments of the present disclosure;FIG. 4 is a top view of a display panel according to some embodiments of the present disclosure;FIG. 5 is a schematic structural diagram of an auxiliary electrode pattern in FIG. 4;FIG. 6 is a top view of a display panel without an auxiliary electrode pattern according to some embodiments of the present disclosure;FIG. 7 is a schematic diagram of a diffraction simulation test on the display panel shown in FIG. 6;FIG. 8 is a schematic diagram of a diffraction simulation test on the display panel shown in FIG. 4;FIG. 9 is a sectional view of a display panel according to some embodiments of the present disclosure;FIG. 10 is a sectional view of another display panel according to some embodiments of the present disclosure;FIG. 11 is a sectional view of yet another display panel according to some embodiments of the present disclosure;FIG. 12 is a sectional view of still another display panel according to some embodiments of the present disclosure;FIG. 13 is a sectional view of still yet another display panel according to some embodiments of the present disclosure;FIG. 14 is a top view of still yet another display panel according to some embodiments of the present disclosure;FIG. 15 is a sectional view of still yet another display panel according to some embodiments of the present disclosure;FIG. 16 is a schematic diagram of auxiliary electrode patterns and a second cathode layer according to some embodiments of the present disclosure;FIG. 17 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure;FIG. 18 is a planar diagram of a sub-pixel in a first display region according to some embodiments of the present disclosure;FIG. 19 is a planar diagram of an active layer of a sub-pixel included in one repeat unit in FIG. 18;FIG. 20 is a planar diagram of a combination of an active layer and a first gate layer of a sub-