EP-4742233-A1 - METHOD FOR REFRESHING DISPLAY IN PARTITIONED MANNER, DISPLAY SYSTEM, AND ELECTRONIC DEVICE

EP4742233A1EP 4742233 A1EP4742233 A1EP 4742233A1EP-4742233-A1

Abstract

A partition refresh method of a display (10), a display system (60), and an electronic device (100) are provided. More enable signal lines are introduced to the display (10), to provide an enable signal for cascaded GOA units (220) for a longer time, thereby providing a condition for increasing a pulse width of a data holding signal output by the GOA unit (220) and creating a non-coupling area. In addition, in the partition refresh method of the display (10), the pulse width of the data holding signal output by the GOA unit (220) is increased, and a data writing control signal is controlled to appear after a coupling area, so that data writing into a pixel unit (210) is not interfered by a glitch of the data holding signal, to avoid a screen horizontal stripe.

Inventors

HAO, Sikun
HE, Hu

Assignees

Huawei Technologies Co., Ltd.

Dates

Publication Date: 20260513
Application Date: 20241108

Claims (20)

A partition refresh method of a display, wherein the display comprises a display circuit, a first gate on array GOA circuit, and a second GOA circuit, the display circuit comprises a plurality of pixel units, the first GOA circuit comprises M*N cascaded first GOA units, the first GOA circuit is connected to M enable signal lines, one enable signal line is connected to N stages of first GOA units, the first GOA unit is configured to output a data holding signal to the pixel unit, the second GOA circuit comprises cascaded second GOA units, the second GOA unit is configured to output a data writing control signal to the pixel unit, M and N are positive integers, and M is greater than or equal to 2; and the method comprises: at a moment h, controlling an initial first GOA unit to output the data holding signal, wherein the data holding signal lasts for X row scanning times, and X>N; and at a moment k, controlling an initial second GOA unit to output the data writing control signal, wherein the moment k is later than a moment h+N*H and earlier than a moment h+X*H, and H indicates one row scanning time.
The method according to claim 1, wherein controlling the initial first GOA unit to output the data holding signal specifically comprises: controlling an i th first GOA unit in the cascaded M*N first GOA units to output the data holding signal at a moment h+(i-1)*Q*H, wherein i is a positive integer, i≤M*N, and Q indicates that the i th first GOA unit outputs the data holding signal Q row scanning times earlier than an (i+1) th first GOA unit.
The method according to claim 1 or 2, wherein controlling the initial first GOA unit to output the data holding signal specifically comprises: inputting a start vertical STV signal to an input end of the initial first GOA unit at a moment h-Q*H, wherein Q indicates that the i th first GOA unit outputs the data holding signal Q row scanning times earlier than the (i+1) th first GOA unit.
The method according to any one of claims 1 to 3, wherein a calculation formula for a maximum value X max of X is as follows: X max =M*Y-(M*N-1)*Q, Y indicates a pulse width of an enable signal on the enable signal line, and Q indicates that the i th first GOA unit outputs the data holding signal Q row scanning times earlier than the (i+1) th first GOA unit.
The method according to any one of claims 1 to 4, wherein controlling the initial second GOA unit to output the data writing control signal specifically comprises: starting, by a j th second GOA unit in the cascaded second GOA units, to output the data writing control signal at a moment k+(j-1)*q, wherein q indicates a time by which the j th second GOA unit outputs the data writing control signal later than a (j-1) th second GOA unit, j is a positive integer, and j is less than or equal to a quantity of the cascaded second GOA units.
The method according to any one of claims 1 to 5, wherein controlling the initial second GOA unit to output the data writing control signal specifically comprises: inputting a start vertical STV signal to an input end of the initial second GOA unit at a moment k-q, wherein q indicates the time by which the j th second GOA unit outputs the data writing control signal later than the (j-1) th second GOA unit.
The method according to any one of claims 1 to 6, wherein the VFE signal is a high-level signal, the data holding signal is also a high-level signal, and the method further comprises: controlling a time at which the enable signal on the enable signal line switches from a high level to a low level to be later than a first time, wherein the first time is a time at which the data holding signal output by a last first GOA unit connected to the enable signal line switches from a high level to a low level.
A partition refresh method of a display, wherein the display comprises a display circuit, a first gate on array GOA circuit, and a second GOA circuit, the display circuit comprises a plurality of pixel units, the first GOA circuit comprises M*N cascaded first GOA units, the first GOA circuit is connected to M enable signal lines, one enable signal line is connected to N stages of first GOA units, the first GOA unit is configured to output a data holding signal to the pixel unit, the second GOA circuit comprises cascaded second GOA units, the second GOA unit is configured to output a data writing control signal to the pixel unit, M and N are positive integers, and M is greater than or equal to 2; and the method comprises: determining a time for performing data writing into a pixel unit in a first screen area; and when performing data writing into the pixel unit in the first screen area, performing first bias processing on a reset voltage of the pixel unit in the first screen area, wherein a reset voltage after the first bias processing is a reset voltage corresponding to a first reference luminance at a first refresh rate during data writing; and the first reference luminance is less than a luminance corresponding to the reset voltage of the pixel unit in the first screen area at the first refresh rate before the first bias processing.
The method according to claim 8, wherein the first reference luminance is specifically a luminance corresponding to a first reset voltage at a second refresh rate during data writing, the first reset voltage is a reset voltage of a pixel unit in a second screen area during data writing into the second screen area under refresh at the second refresh rate, and the second refresh rate is higher than the first refresh rate.
The method according to claim 9, further comprising: obtaining the first reset voltage through measurement.
The method according to claim 9 or 10, wherein the second screen area is a screen area with a highest refresh rate.
The method according to any one of claims 8 to 11, further comprising: searching a first mapping table for a luminance corresponding to the first reset voltage, and determining the found luminance as the first reference luminance; and searching a second mapping table for a reset voltage corresponding to the first reference luminance, and determining the found reset voltage as the reset voltage after the first bias processing, wherein the first mapping table is used to record a correspondence between a reset voltage and a luminance during data writing at the second refresh rate, and the second mapping table is used to record a correspondence between a reset voltage and a luminance during data writing at the first refresh rate.
A partition refresh method of a display, wherein the display comprises a display circuit, a first gate on array GOA circuit, and a second GOA circuit, the display circuit comprises a plurality of pixel units, the first GOA circuit comprises M*N cascaded first GOA units, the first GOA circuit is connected to M enable signal lines, one enable signal line is connected to N stages of first GOA units, the first GOA unit is configured to output a data holding signal to the pixel unit, the second GOA circuit comprises cascaded second GOA units, the second GOA unit is configured to output a data writing control signal to the pixel unit, M and N are positive integers, and M is greater than or equal to 2; and the method comprises: determining a time for skipping performing data writing into a pixel unit in a third screen area, wherein a refresh rate of the third screen area is a third refresh rate; and when skipping performing data writing into the pixel unit in the third screen area, performing second bias processing on a reset voltage of the pixel unit in the third screen area, wherein a reset voltage after the second bias processing is a reset voltage corresponding to a second reference luminance at the third refresh rate during data holding; and the second reference luminance is a luminance corresponding to a second reset voltage at the third refresh rate during data writing, and the second reset voltage is a reset voltage during data writing into the third screen area at the third refresh rate.
The method according to claim 13, further comprising: obtaining the second reset voltage through measurement.
The method according to claim 13 or 14, further comprising: determining a time for performing data writing into the pixel unit in the third screen area.
The method according to any one of claims 13 to 15, further comprising: searching a third mapping table for a luminance corresponding to the second reset voltage, and determining the found luminance as the second reference luminance; and searching a fourth mapping table for a reset voltage corresponding to the second reference luminance, and determining the found reset voltage as the reset voltage after the second bias processing, wherein the third mapping table is used to record a correspondence between a reset voltage and a luminance during data writing at the third refresh rate, and the fourth mapping table is used to record a correspondence between a reset voltage and a luminance during data holding at the third refresh rate.
The method according to any one of claims 13 to 16, wherein the third screen area is specifically the first screen area, and the third refresh rate is specifically the first refresh rate; and before performing the second bias processing, the method further comprises: determining a time for performing data writing into a pixel unit in the first screen area; and when performing data writing into the pixel unit in the first screen area, performing first bias processing on a reset voltage of the pixel unit in the first screen area, wherein a reset voltage after the first bias processing is a reset voltage corresponding to a first reference luminance at the first refresh rate during data writing; and the first reference luminance is specifically a luminance corresponding to a first reset voltage at a second refresh rate during data writing, the first reset voltage is a reset voltage of a pixel unit in a second screen area during data writing into the second screen area under refresh at the second refresh rate, and the second refresh rate is higher than the first refresh rate.
The method according to claim 17, further comprising: obtaining the first reset voltage through measurement.
The method according to claim 17 or 18, wherein the second screen area is a screen area with a highest refresh rate.
The method according to any one of claims 17 to 19, further comprising: searching a first mapping table for a luminance corresponding to the first reset voltage, and determining the found luminance as the first reference luminance; and searching a second mapping table for a reset voltage corresponding to the first reference luminance, and determining the found reset voltage as the reset voltage after the first bias processing, wherein the first mapping table is used to record a correspondence between a reset voltage and a luminance during data writing at the second refresh rate, and the second mapping table is used to record a correspondence between a reset voltage and a luminance during data writing at the first refresh rate.

Description

This application claims priority to Chinese Patent Application No. 202311554390.2, filed with the China National Intellectual Property Administration on November 17, 2023, and entitled "PARTITION REFRESH METHOD OF DISPLAY, DISPLAY SYSTEM, AND ELECTRONIC DEVICE", which is incorporated herein by reference in its entirety. TECHNICAL FIELD This application relates to the field of electronic technologies, and in particular, to a partition refresh method of a display, a display system, and an electronic device. BACKGROUND With development of display technologies, to ensure smooth display of a picture, screen refresh rates supported by electronic devices such as mobile phones and tablet computers are continuously increased. However, power consumption of displays poses a great challenge to power saving or battery lives of the devices. To address this, displays that support a low refresh rate or even an ultra-low refresh rate are gradually introduced to the market in recent years, for example, low-temperature polycrystalline oxide (low-temperature polycrystalline oxide, LTPO) displays that support a refresh rate down to 1 Hz. Nevertheless, a current refresh manner of a display component is full-screen refresh. When only a small part of a picture on a screen needs to be updated, a display driver integrated circuit (display driver integrated circuit, DDIC) still refreshes the entire picture on the screen, resulting in unnecessary power consumption. SUMMARY Embodiments of this application provide a partition refresh method of a display and an electronic device, to resolve one or more problems such as a screen horizontal stripe, a luminance difference between a low refresh area and a high refresh area, and screen flickering while a partition variable frequency function is supported. According to a first aspect, an embodiment of this application provides a partition refresh method of a display. The method may be applied to the display. The display may include a display circuit, a first gate on array GOA circuit, and a second GOA circuit, a display panel includes a plurality of pixel units, the first GOA circuit includes M*N cascaded first GOA units, the first GOA circuit is connected to M enable signal lines, one enable signal line is connected to N stages of first GOA units, the first GOA unit is configured to output a data holding signal to the pixel unit, the second GOA circuit includes cascaded second GOA units, the second GOA unit is configured to output a data writing control signal to the pixel unit, M and N are positive integers, and M is greater than or equal to 2. The method may include: at a moment h, controlling an initial first GOA unit to output the data holding signal, where the data holding signal lasts for X row scanning times, and X>N; andat a moment k, controlling an initial second GOA unit to output the data writing control signal, where the moment k is later than a moment h+N*H and earlier than a moment h+X*H, and H indicates one row scanning time. In the first aspect, the display may be the display 10 mentioned in subsequent embodiments, the display circuit, the first GOA circuit, and the second GOA circuit may be the display circuit 21, the GOA circuit 22, and the GOA circuit 23 mentioned in subsequent embodiments, and the first GOA unit and the second GOA unit may be the GOA unit 220 and the GOA unit 230 mentioned in subsequent embodiments. According to the method provided in the first aspect, more enable signal lines are introduced to the display 10, so that enable signals may be provided for cascaded GOA units 220 for a longer time, to provide a condition for increasing a pulse width of a data holding signal S1 and creating a non-coupling area. In addition, a pulse width of the data holding signal S1 is at least greater than N row scanning times, to ensure that a pulse width of a data holding signal S1 output by each GOA unit 220 includes a non-coupling area. In addition, the moment k is later than the moment h+N*H, so that a data writing control signal G1 may appear after a coupling area of the data holding signal S1, so that data writing into the pixel unit is not affected by a glitch of S1, and no screen horizontal stripe appears. With reference to the first aspect, in some embodiments, controlling the initial first GOA unit to output the data holding signal may specifically include: controlling an ith first GOA unit in the cascaded M*N first GOA units to output the data holding signal at a moment h+(i-1)*Q*H, where i is a positive integer, i≤M*N, Q indicates that the data holding signal S1 output by the ith GOA unit 220 is Q row scanning times earlier than a data holding signal S1 output by an (i+1)th GOA unit 220, and a value of Q may be a positive integer, for example, 1 or 2. With reference to the first aspect, in some embodiments, controlling the initial first GOA unit to output the data holding signal may specifically include: inputting a start vertical STV signal to an input end of the